6502.org Forum  Projects  Code  Documents  Tools  Forum
It is currently Fri Sep 27, 2024 9:28 am

All times are UTC




Post new topic Reply to topic  [ 91 posts ]  Go to page Previous  1, 2, 3, 4, 5 ... 7  Next
Author Message
PostPosted: Wed Feb 13, 2013 5:43 am 
Offline
User avatar

Joined: Thu May 28, 2009 9:46 pm
Posts: 8402
Location: Midwestern USA
Dr Jefyll wrote:
BigDumbDinosaur wrote:
I am suspect of the published '816 timing specs for several reasons, not the least of which is my observations on POC V1 at various Ø2 frequencies indicate that the timings seem to be proportional, not fixed, as the specs seem to imply. Also, Garth Wilson has often pointed out that the data sheets for the various WDC devices tend to paint a conservative (sometimes gloomy) picture of their capabilities.
It's quite plausible to say the published figures are conservative, but to say that in reality the actual delays scale proportionally with clock speed is a provocative statement -- I got derailed on that one!

So it would seem. I imagine the internal prop time through the gates is vanishingly small but cummulative (MPU design is not my area of expertise).

Quote:
Quote:
In any case, I've tested with Ø2 at 1, 4, 8, 12.5 and 15 MHz, and have noted that the bus timings as a percentage of machine cycle time don't change much, especially the all-important tBH bank address hold time.
What else did you test besides tBH?

Just tBH. That is the most stringent timing value that must be considered in a real-world design.

Quote:
Is this diagram a reasonable representation of what you used? (I like simple tests.)

Not quite. The NOP part drives D0-D7 through a 74ABT541 buffer, which is gated to the high-Z state when Ø2 is low, thus preventing bus contention. The balance of the circuit is the same. I used the buffer to simulate what would happen in a real application. It's prop time input to output is 2.6 to 2.9ns. I'll dig up the schematic some time and post it.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!


Top
 Profile  
Reply with quote  
PostPosted: Wed Feb 13, 2013 9:19 am 
Offline
User avatar

Joined: Fri Dec 11, 2009 3:50 pm
Posts: 3367
Location: Ontario, Canada
Quote:
I've tested with Ø2 at 1, 4, 8, 12.5 and 15 MHz, and have noted that the bus timings as a percentage of machine cycle time don't change much, especially the all-important tBH bank address hold time.
Quote:
What else did you test besides tBH?
Quote:
Just tBH. That is the most stringent timing value that must be considered in a real-world design.

When you report about "the bus timings" -- and even center one out for special attention ("especially the all-important tBH") -- readers are left with the impression that tBH was just one of a list of values included in your analysis. Aren't you maybe kinda stretching things? What's up with that? You have a nice prose style when you write, but knowing when to stop is a valuable skill, too. I'm trying to say that in a nice way, even though this is via email (sort of).

Be that as it may, hats off to you for actually performing some sort of experiment. It's something I wanted to do myself and haven't gotten around to. :|

cheers,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html


Top
 Profile  
Reply with quote  
PostPosted: Thu Feb 14, 2013 5:09 am 
Offline
User avatar

Joined: Thu May 28, 2009 9:46 pm
Posts: 8402
Location: Midwestern USA
Dr Jefyll wrote:
When you report about "the bus timings" -- and even center one out for special attention ("especially the all-important tBH") -- readers are left with the impression that tBH was just one of a list of values included in your analysis. Aren't you maybe kinda stretching things? What's up with that? You have a nice prose style when you write, but knowing when to stop is a valuable skill, too. I'm trying to say that in a nice way, even though this is via email (sort of).

Be that as it may, hats off to you for actually performing some sort of experiment. It's something I wanted to do myself and haven't gotten around to. :|

cheers,
Jeff

Sorry if I gave the impression that I was observing a laundry-list of items. tBH was the only one to which I was paying close attention. However, I also watched RWB, VDA and VPA to see what they were up to with different speeds. I didn't see anything that I didn't expect to see.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!


Top
 Profile  
Reply with quote  
PostPosted: Thu Feb 14, 2013 5:58 pm 
Offline
User avatar

Joined: Fri Dec 11, 2009 3:50 pm
Posts: 3367
Location: Ontario, Canada
Well, it's an interesting subject. If you do collect some detailed information I hope you'll share it with us.
BigDumbDinosaur wrote:
Most of the ABT and FCT series are produced in SMT packages, many being SOIC (50 mil). You won't find much in PDIP, but I don't see that as a limitation anymore. The SOIC packages are easily hand-soldered. If I can do it, all you younger guys certainly can! :P
Easily hand-soldered? Heck, you're doing better than I am if "easy" is the word that comes to mind! But the .050" stuff is do-able.

Although it's slightly off-topic, I will quickly mention that proto-board using .050" grid is available. Unfortunately the selection is very limited; I know of only two examples, the Vector 8021 and the 8028. The 8028 is actually a combo board with areas of .100", .050" and 2mm grid.

cheers,
Jeff


Attachments:
Vector 8028.JPG
Vector 8028.JPG [ 104.89 KiB | Viewed 3933 times ]

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
Top
 Profile  
Reply with quote  
PostPosted: Thu Feb 14, 2013 6:56 pm 
Offline
User avatar

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8520
Location: Southern California
Dr Jefyll wrote:
Although it's slightly off-topic, I will quickly mention that proto-board using .050" grid is available. Unfortunately the selection is very limited; I know of only two examples, the Vector 8021 and the 8028. The 8028 is actually a combo board with areas of .100", .050" and 2mm grid.

Twin Industries has them too, and they tend to be much, much cheaper than Vector. I saw them at the local Fry's Electronics. See https://twinind.com/index.php/products/ ... ng-boards/ . The holes on .050" centers are too small to put regular WW sockets into though. Another alternative if you really don't want to make a custom board is to use the SOIC-to-DIP adapters. They tend to be expensive; but buying several would still be a lot cheaper than getting a PC board made.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


Top
 Profile  
Reply with quote  
PostPosted: Thu Feb 14, 2013 9:28 pm 
Offline

Joined: Sat Oct 20, 2012 8:41 pm
Posts: 87
Location: San Diego
I have used the WDC schematic for bank latching using an ACT573 and the ACT245 and had stable operation with a 10mhz clock. The rest of the glue logic was HCT based and the circuit was wire wrapped. Just keep the wires as short as possible and use plenty of bypass caps. (soldered in if possible) as close to the chips as you can get.


Top
 Profile  
Reply with quote  
PostPosted: Thu Feb 14, 2013 10:26 pm 
Offline
User avatar

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10938
Location: England
Hi Clockpulse - good to hear about your success. Could you comment please on how short your wires are and close the caps are to the chips? I prefer to see "a few inches" and "less than half an inch" to "as close as possible", because it's much more helpful to anyone without the experience.

Thanks!
Ed


Top
 Profile  
Reply with quote  
PostPosted: Thu Feb 14, 2013 11:19 pm 
Offline

Joined: Sat Oct 20, 2012 8:41 pm
Posts: 87
Location: San Diego
BigEd wrote:
Hi Clockpulse - good to hear about your success. Could you comment please on how short your wires are and close the caps are to the chips? I prefer to see "a few inches" and "less than half an inch" to "as close as possible", because it's much more helpful to anyone without the experience.


It's not easy to keep the leads on the caps. short when using wire wrap sockets but I try to keep them right next to the socket or between sockets with a distance less than half an inch. Supply and Ground rails help. In some cases I have soldered the caps on the bottom straight between the Vcc and gnd pins of the chip (best for buffer drivers like the 245).

I 'try' to keep the wire wrap wires in the 2 to 3 inch range. Of course when you're running the data and address busses the total length might add up to 6 or 7 inches. A board with a ground plane helps, and keep the wires against the board.


Top
 Profile  
Reply with quote  
PostPosted: Fri Feb 15, 2013 8:05 am 
Offline
User avatar

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10938
Location: England
Thanks!


Top
 Profile  
Reply with quote  
PostPosted: Sun Mar 03, 2013 2:34 pm 
Offline
User avatar

Joined: Tue Nov 16, 2010 8:00 am
Posts: 2353
Location: Gouda, The Netherlands
BigEd wrote:
On a separate note, I wonder if the '802 drives the bus during phi1 - I'd bet that it is the same die, with a different bond-out.)

According to WDC's Programming the 65816 it's a very similar die, but with differences in the metal layer(s):
Quote:
The 65816 and the 65802 were designed to bring the 65x family into line with the current generation of advanced processors. First produced in prototypes in the second half of 1984, they were released simultaneously early in 1985. The 65816 is a full-featured realization of the 65x concept as a sixteen-bit machine. The 65802 is its little brother, with the 65816’s sixteen-bit processing packaged with the 6502’s pinout for compatibility with existing hardware.

The two processors are quite similar. They are, in fact, two different versions of the same basic design. In the early stages of the chip fabrication process they are identical and only assume their distinct “personalities” during the final (metalization) phase of manufacture.


Top
 Profile  
Reply with quote  
PostPosted: Sun Mar 03, 2013 3:27 pm 
Offline
User avatar

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10938
Location: England
I stand corrected - thanks!


Top
 Profile  
Reply with quote  
PostPosted: Sun Mar 03, 2013 8:20 pm 
Offline
User avatar

Joined: Thu May 28, 2009 9:46 pm
Posts: 8402
Location: Midwestern USA
Arlet wrote:
BigEd wrote:
On a separate note, I wonder if the '802 drives the bus during phi1 - I'd bet that it is the same die, with a different bond-out.)

According to WDC's Programming the 65816 it's a very similar die, but with differences in the metal layer(s):
Quote:
The 65816 and the 65802 were designed to bring the 65x family into line with the current generation of advanced processors. First produced in prototypes in the second half of 1984, they were released simultaneously early in 1985. The 65816 is a full-featured realization of the 65x concept as a sixteen-bit machine. The 65802 is its little brother, with the 65816’s sixteen-bit processing packaged with the 6502’s pinout for compatibility with existing hardware.

The two processors are quite similar. They are, in fact, two different versions of the same basic design. In the early stages of the chip fabrication process they are identical and only assume their distinct “personalities” during the final (metalization) phase of manufacture.

In the past, I had a 65C802 [corrected from 65C02] data sheet here but I think I tossed it during one of my periodic "clean up the office" fits. I do recall that the bank address MUXing was not present on the 65C802, as the '802 was required to be an exact in-circuit replacement for the 65C02. Had the MUXing been present there would have been data bus contention on each valid memory cycle when Ø2 was low. Also missing were the 65C816's VDA and VPA address bus qualification outputs. Their omission strongly suggested that something had to have been done to prevent the false address bus states that the '816 generates during certain stages of some instructions, especially those with <addr>,X and <addr>,Y addressing.

I never have worked with the '802, but ironically did have an opportunity do so years ago when I was developing firmware for a 65C02-powered terminal concentrator. As the '802 was a drop-in replacement for the 'C02 I could have obtained an '802 from WDC and plugged it in. However, the job required 'C02 compatibility, meaning no 16 bit code, and time was of the essence. So the opportunity was not taken. :cry:

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!


Last edited by BigDumbDinosaur on Mon Mar 04, 2013 4:36 pm, edited 1 time in total.

Top
 Profile  
Reply with quote  
PostPosted: Sun Mar 03, 2013 10:02 pm 
Offline
User avatar

Joined: Tue Nov 16, 2010 8:00 am
Posts: 2353
Location: Gouda, The Netherlands
Indeed. The same document I linked to makes it clear that the '802 is circuit compatible, and that it doesn't have the bank address when phi2 is low (limiting it to 64KB):
Quote:
This makes the 65802 a unique, pin-compatible, software-compatible sixteen-bit upgrade chip. You can pull a 6502 out of its socket in any existing 6502 system, and replace it with a 65802 because it powers-on in the 6502 emulation mode. It will run existing applications exactly the same as the 6502 did. Yet new software can be written, and 6502 programs rewritten, to take advantage of the 65802’s sixteen-bit capabilities, resulting in programs which take up much less code space and which run faster. Unfortunately, even with a 65802 installed, an older system will remain unable to address memory beyond the original 64K limits of the 6502. This is the price of hardware compatibility


Top
 Profile  
Reply with quote  
PostPosted: Wed Mar 06, 2013 3:01 am 
Offline
User avatar

Joined: Fri Dec 11, 2009 3:50 pm
Posts: 3367
Location: Ontario, Canada
BigDumbDinosaur wrote:
Also missing were the 65C816's VDA and VPA address bus qualification outputs. Their omission strongly suggested that something had to have been done to prevent the false address bus states that the '816 generates during certain stages of some instructions, especially those with <addr>,X and <addr>,Y addressing.
Interesting point, well worth mentioning. Still, do we conclude that "something had to have been done," or, "it would have been nice if something had been done"?

If the '816 and '802 are the same basic die, differing only in some of the metalization, it doesn't seem plausible that invalid-address cycles would appear (as we know they do) on the '816 but not on the '802. What seems more likely to me is that the '802 also exhibits the invalid-address cycles, and, since VPA and VDA outputs are absent, this is a hazard with no good solution. IOW, people using the '802 would need to be on guard against the possibility that an invalid address would read from an IO device, which, on some devices, can erroneously alter status.

Odd (and disappointing) as this seems, it doesn't contradict the definition of the '802 as a drop-in replacement for an NMOS 6502, since the latter exhibits the same hazardous behavior. (Or was the '802 touted as a drop-in replacement for the 'C02 as well?)

cheers,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html


Top
 Profile  
Reply with quote  
PostPosted: Thu Mar 07, 2013 2:18 am 
Offline

Joined: Sat Oct 20, 2012 8:41 pm
Posts: 87
Location: San Diego
Dr Jefyll wrote:
BigDumbDinosaur wrote:
Also missing were the 65C816's VDA and VPA address bus qualification outputs. Their omission strongly suggested that something had to have been done to prevent the false address bus states that the '816 generates during certain stages of some instructions, especially those with <addr>,X and <addr>,Y addressing.
Interesting point, well worth mentioning. Still, do we conclude that "something had to have been done," or, "it would have been nice if something had been done"?

If the '816 and '802 are the same basic die, differing only in some of the metalization, it doesn't seem plausible that invalid-address cycles would appear (as we know they do) on the '816 but not on the '802. What seems more likely to me is that the '802 also exhibits the invalid-address cycles, and, since VPA and VDA outputs are absent, this is a hazard with no good solution. IOW, people using the '802 would need to be on guard against the possibility that an invalid address would read from an IO device, which, on some devices, can erroneously alter status.

Odd (and disappointing) as this seems, it doesn't contradict the definition of the '802 as a drop-in replacement for an NMOS 6502, since the latter exhibits the same hazardous behavior. (Or was the '802 touted as a drop-in replacement for the 'C02 as well?)



Back in the mid 80's I did swap the 65c02 in an apple IIe for the 802 and it worked fine. The Merlin 8/16 assembler I used at that time had an option that would actually use the 802 instructions to enhance Merlin's performance.


Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 91 posts ]  Go to page Previous  1, 2, 3, 4, 5 ... 7  Next

All times are UTC


Who is online

Users browsing this forum: No registered users and 13 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to: