visual6502 Q: Trying to understand every transistor.

[cerebrum]

Hi,

in case you are wondering why I'm asking so many questions on this board, it's because I've become obsessed with understanding what every transistor in the 6502 does. I think visual6502 is a great opportunity to really understand a processor and my interest was piqued by this blog post:

http://www.righto.com/2013/01/a-small-p ... ained.html

So in the last days I started to get the hang of it and managed to follow the workings of the 6502 from the databus until the IR. Now I'm coming to the decode ROM and realize that it is a logical quagmire. Each of the 130 lines leads to some piece of control logic and from there other transistors propagate, etc...

Questions:

1 Is it really worth it doing all this work. I wonder whether the hypothetical insights I will gain are worth the effort.
2 What is the best way to wade through this quagmire, has anyone done this at all?

I'm grateful for any other suggestions, inspirations, etc...

[BigEd]

I'm sure it's worth understanding the 6502 at a slightly higher level: the 'why' or 'what' rather than the 'how' - complex logic equations can capture a dozen transistors in a single line. I believe Segher has written such equations and possibly even simulated them, but I can't find them in any public place. His website is http://segher.ircgeeks.net/ but it's not traversable. You could mail him at the publicly discoverable segher at kernel dot crashing dot org.

What I did find was http://bisqwit.iki.fi/kala/nes-pla-listing.txt where someone has tabulated which 6502 instructions activate the various PLA outputs. That's worth understanding. But the next area, the random logic, is a cloud of magic. The outputs of the random logic: the datapath controls and the various bits of state, are worth understanding.

You should also check out the thread viewtopic.php?f=8&t=2208 (Breaking 6502 apart) and the associated project at http://code.google.com/p/breaks/

Cheers
Ed

[cerebrum]

BigEd, I emailed Segher at the provided address but got no response so far.

I'm wondering what might be the best tool/technique to visually organize the processor? Would something like a Semantic network or a Concept map be helpful? Or are there specific tools for this task?

I'm thinking about writing down all logic equations that govern the 6502. This would be one level above the transistors.

[BigEd]

It would be great to have a public and debugged set of equations! Donald Hanson wrote up equations for the 6522, which make for a compact representation.

There's a difficulty with equations, just as with simulation, which is the bidirectional pass gates which connect the busses. Cause and effect flow in both directions, depending on the datapath operation.

I think the "Breaks" project's approach, which has produced a coloured map of the logic, is promising. If those patches are indeed relatively isolated, each one could be described independently, and the outputs should have meaningful functions which could be named descriptively.

It's appealing to keep close to the original layout: it will, to some extent, minimise long-distance connections and clump together related gates. Balazs' schematic and Breaks' colouring should both be helpful.

Take a look too at a couple of threads by "Xor" who was tackling the same kind of project:
viewtopic.php?p=13216#p13216
viewtopic.php?f=10&t=1747

Cheers
Ed

[BigEd]

(See the files in the Breaks project at http://code.google.com/p/breaks/source/ ... Freversing )
(See Segher's notes on the datapath at http://visual6502.org/wiki/index.php?ti ... 2_datapath )

[cerebrum]

One thing I didn't mention up to now is why I want to understand the 6502. The reason is that I'm actually a programmer and a processor would be one example of programming at the lowest level(transistor/logic gate level). I hope to get some good insights about programming, including programming in parallel since what happens in the processor is inherently parallel(electricity flows simultaneously through all connections).

Do you think this hope is misguided or the hypothetical gain not worth the effort?

[BigEd]

You certainly learn something extra by programming at the machine level, and even more if you design your own machine! So, deeply understanding a machine implementation would be somewhere in between those two.

You may get a feel for the costs of certain things, but you won't see all the tradeoffs which had to occur during design, because some of them will be missing!

Over on anycpu.org, Jeff posted some good pointers about CPU design: I recommend you take a look.
http://anycpu.org/forum/viewtopic.php?f=3&t=23#p84

Cheers
Ed

[White Flame]

If you want that level of detail just as a learning experience, there is a free online course exactly for that. It starts at NAND gates, and goes all the way up to programming Tetris on a processor you build from the ground up.

http://www.nand2tetris.org/course.php

I haven't gone through it myself, so I can't vouch for its actual quality, though I'm meaning to and the few things I've heard about it have all been positive.

[BigEd]

Likewise, I hear good things about nand2tetris!

[cerebrum]

Yep, I knew about nand2tetris and had previously looked at it but dismissed it as too simplistic. Maybe I should reconsider.

[Arlet]

Another idea is to try out FPGAs and study a CPU core, or even write one yourself. A modern Verilog/VHDL implementation is easier to understand than a few thousand transistors.

[BigEd]

I think nand2tetris addresses the question of how do CPUs work. Jeff's pair of resources address the question of what tradeoffs to make in an implementation that has a goal (such as performance, or size)

Agreed, the FPGA world is a good world to work in: you don't even need an FPGA, as the free tools include simulators.

Cheers
Ed