[97] Interrupt timing
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ThomasHarte
[97.1] Interrupt timing
Just a small question from an emulator author - how come (maskable) interrupts take 7 cycles? Presumably the final five cycles are 'push pc low byte / push pc high byte / push status register / load new pc low byte / load new pc high byte' (give or take the ordering of the first three), but what are the first two concerned with? Not even 64doc seems to have this information.
[97.2] Interrupt timing
ccording to my Rockwell book, there are 8 cycles involved in the NMI.
1 Fetch OP Code Hold Prog. Ctr, Finish Prev Operation
2 Fetch OP Code Hold Prg Ctr
3 Push PCH Decrement Stack Pointer
4 Push PCL Decrement Stack Pointer
5 Push Processor Status Decrement Stack Pointer
6 Fetch Vector Low ($FFFA) Load to PC Low
7 Fetch Vector High ($FFFB) Load to PC High
8 Fetch Interrupt Program Increment PC to PC+1
Hope this helps
Ted Melton
1 Fetch OP Code Hold Prog. Ctr, Finish Prev Operation
2 Fetch OP Code Hold Prg Ctr
3 Push PCH Decrement Stack Pointer
4 Push PCL Decrement Stack Pointer
5 Push Processor Status Decrement Stack Pointer
6 Fetch Vector Low ($FFFA) Load to PC Low
7 Fetch Vector High ($FFFB) Load to PC High
8 Fetch Interrupt Program Increment PC to PC+1
Hope this helps
Ted Melton