I understood that the feedback cycle is only active when Cp2(phi2) is on. But when phi2 is down and the cpu is not writing to the register the feedback cycle is interrupted and the result should be that the stored bit will immediately become 0. Or is there a timing issue here in that phi2 will be down only a very short time, not enough for the feedback cycle to "notice"?
Last edited by cerebrum on Wed Feb 06, 2013 7:50 pm, edited 1 time in total.
Because the two gates are inverting each other's output, the circuit is bistable even with feedback on - it doesn't collapse to '0'
But, in the presence of feedback, to write into such a cell you need a strong drive on both true and false bitlines: this is what AMD's 8085 does in the register file. So, interrupting the feedback during not-phi2 allows a single-ended write signal.
I think the question is: why is the storage of the bit retained, even when phi2 is not high ? The answer is that the phi2 is only '0' for a short period, and as long as the 'write' signal is not asserted, the stray capacitance of the transistors holds the value. That's why the NMOS 6502 has a minimum clock frequency. If you would keep the phi2=0 for a longer time, the charge would leak away and the storage element could flip.
