Hi Cerebrum, and welcome!
Yes indeed, phi1 and phase1 are the same things. Sometimes people use the Greek Phi character: Φ and φ for uppercase and lowercase respectively.
On the top edge of the 6502, as viewed in visual6502, you'll find the third pad from the right is clk0 which would be bonded to the phi0 clock input pin (and next to it the pad for cclk which is not connected for 6502 but is (surely) the direct input of the phase2 on-chip clock in the 6501.) This phi0 pin is marked as p0 in your schematic extract.
http://visual6502.org/JSSim/expert.html?find=clk0Most of the clocking on the chip is done by two signals: called cp1 and cclk in visual6502. cp1 is phase 1 and cclk is phase 2. Visual6502 simulates only at the clock phase level of granularity, so it can't show the small delays between the successive stages of buffers or inverters. As your schematic extract shows, the phi2 drive circuit uses a NOR gate to ensure that it's low when phi1 is high.
Disregarding small delays, we have just two phases with several names:
phi0 AKA clk0 AKA p0, all same phase as phi2 AKA cclk AKA cp2 AKA p2
phi1, cp1 AKA p1.
Note that nodes 43 and 1247 which control some of the datapath control signals are also directly derived from cp1, so they are somewhat like phi2 but with some difference in timing.
Hope this helps
Ed