But not the 1.2V regulator; the primary current needed by the FPGA is in that power supply. Whether it is run in series or in parallel, DeltaV for the +1.2V linear is a bit high for my taste; the effective voltage drop is 3.8V. Most of the static current in the FPGA is found in the +1.2V power circuit. If it is run in series, then its current also flows through the +3.3V regulator increasing its power dissipation as well.

I can't tell how the two regulators are connected: in series or in parallel. I like the simplicity of linear regulators, but pours attached to their power pads are not generally sufficient in my estimation to prevent thermal limiting. The larger FPGA will encourage experimentation with ever larger, more complex circuits. This alone almost requires the use of a four layer card in order to avoid difficult to diagnose power supply problems as the experiments being conducted with this fine little card exceed the capabiliities of the power system.

Enso:

BTW. Before production, my customer used a place in CO to assemble the prototypes. I've used the same company for assembling prototypes with BGAs of this size. Smaller BGA like that of the XC3S200AN, the FT256 package, we may do in our little three zone oven or with careful use of our HAAKKO hot air rework station. Something to consider, since the XC3S700AN is about $50 at Digi-Key.

I know that you have some of these parts already, and are likely very familiar with their assembly, but the place only charged my customer and my company something about what we pay our technician per hour to assemble each board. And all the boards delivered back to us worked. The only problems we had was in the hand placed and assembled components we installed ourselves because of a false sense of economy.

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Michael A.

A simple solution could be to bring out the +1.2V supply to a header pin. In case somebody wants to implement fast and complex logic inside the FPGA, the regulator can be removed from the board, and it can be powered externally.

Note that you don't need much logic to emulate retro computer hardware, and it doesn't need to run very fast either.

Enso:


The DCMs in Banks 1 and 3 only drive clock distribution networks which are restricted to the left and right half of the device, respectively. The DCMs in Banks 0 and 2 drive clock distribution networks that span the entire device. With single-ended clocks, only the pins marked as 'P' are directly connected to the IBUFG and BUFGMUXes. Therefore, using those pins provides greater flexibility in how the clocks are connected to DCMs and/or the global clock distribution nets inside the part.

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Michael A.

Arlet:

That is a good solution: allowing either or both linear regulators to be externally supplied.

On the matter of retro-computer hardware, I've followed you, BigEd, and EEyE in your 65Org16 and video efforts over in the Programmable Logic part of the forum. Those efforts have long left the domain of low speed retro-computing hardware. The fact that the FPGAs can support 100 MHz+ operation is simply too tempting.

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Michael A.

On the matter of speed, I would bet the WDC65C02 top speed would be closer to 14MHz @3.3V in the real world apart from the datasheet.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

True, but the boards we've used only have SOT-223 regulators on them.

only? . Those MCP1826's are good for 1amp!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Yeah, but that's only the current. In practice, these devices are limited by power dissipation.

I've done a lot of work with fast clocks on a XESS XC3S1000 board. The tiny regulator is crowded in and gets really hot, but I've never had a thermal shutdown. I will definitely pour some metal around the regulators.

A 4-layer board would definitely be an improvement. Next time. I am curious to see how far 2-layer can be pushed.

Sacrificing an edge connector pin to 1.2V is a pretty good idea.

Both regulators are connected to 5V in parallel. Originally I had the 1.2V regulator suck juice off 3.3V, but I was worried that the sequencing on power-up would be a problem (1.2V should be up before 3.3V), so I just connected both to 5V.

Thanks for the tip about the clocking. There is a lot of space between the regulators for the oscillator near bank0 or 2. I was hoping to keep the crystal away from the regulators, but I think it's OK.

For any quantity I would farm it out, but I don't expect to make more than a handful. I expect something to go wrong at least once with the board layout anyway. Just got the PID controller and some aluminium blocks for the 2-heater hotplate - that should make it easier to fine-tune the process. I'll start a new thread for that project when I have some pictures.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Another thought.

I don't generally use the DCMs, and I let the tools insert the clock buffers. However, I've been working recently on an FPGA implementation of the W65C02S, i.e. wrapping the M65C02 core with a memory interface, vector interrupt controller, clock generator, etc. Yesterday I re-read the DCM portion of the Spartan-3 datasheet, and I noticed that the lower limit for the DCM is now 5 MHz, instead of the 24-25 MHz lower limit of the Spartan-II and Virtex FPGA families. It also indicates that the lower limit is 200 kHz if the DCM clock skew control features are not used, and the DCM is only used in its Digital Frequency Synthesizer (DFS) mode.

For this project, that may be something to consider. In other words, since the processor is not connected directly to ROM/RAM, but all connections run through the FPGA, then the oscillator should not supply the processor directly. Instead, the processor should be supplied from the FPGA using an output from the DCM. In this manner, you can use a higher frequency oscillator to stay above the minimum input frequency of the DCM, and either use the internal frequency synthesizer of the DCMs or a simple even divider in the FPGA fabric to divide the clock down to 1 MHz or any other frequency.

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Michael A.

Recom and CUI (in Digi-Key) make some 78xx-series switchers as linear regulator replacements. I use a Recom product in one of my commercial products, but the CUI device (5V-18V input, +3.3V@1A) appears to require a footprint of 0.6"x0.5" (about the size of an SOT-223 component) and a 10uF input capacitor; I may have to reconsider my continued use of the Recom product if a redesign is required.

If you used such a device, then you can provide +3.3V to the linear, and almost halve the +1.2V LDO's power dissipation. For my XC3S1400AN design I use a custom DC-DC regulator using a Microchip device. The 5V input is switched down to +3.3V, and a linear driven by that supply is used to generate the core voltage. The design uses a MicroBlaze in the FPGA, all of the Block RAM, and an SMSC Ethernet PHY (connected to the MicroBlaze Ethernet MAC-Lite). The regulators are not warm to the touch.

I hate being branded with the logos on the ICs as I'm probing the components with a finger when things don't work properly, so I really like for the regulators to be cool. Just a bit of a wuss in that regard.


I don't like for the supplies to be way out of sequence, but the Spartan-3AN is not sensitive to the power sequencing.

The 5mil trace required to fan out the signals from the inner rows (BTW: very nice fanout of the FPGA) should be sufficient to snake a signal from one of the Bank 1/3 clock pins over to a Bank 0/2 clock pin. Multiple connections will not hurt. There's no reason that you have to move the oscillator. However, moving it will allow you to implement the recommendation I made earlier about the FPGA driving the processor clock input instead of the oscillator.

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Michael A.

Clocking the WDC chip

The WDC socket clock is supplied by the FPGA. I just realized another loose end - are there any pin limitations for outputting a clock from the DCM out? I haven't thought of that; right now PHI2 is connected to FPGA pin W2...

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I moved the oscillator to bank0. I tried running a 5mil line across the FPGA, but didn't like it. I would have to either zig-zag the line and am not sure what it will do to signal reflections, with all the 90-degree turns, or run it across 6 or so unused FPGA pads, which would connect to the input buffers. I don't know what that would do to the clock either. So I just moved it. It's closer to the heat of the 3.3V regulator, but I will look at that next.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Back side of the board, after moving the oscillator and pouring some copper around the regs. 1.2V connected to a pin as Arlet suggested. Michael, I am taking your advice about the switcher seriously and that's next on my agenda.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Not that I am aware of. The only thing that I don't like about the Spartan-3AN family is its input-only pins. If you had to generate the symbol and pattern for any of these parts, you will need to run through the spreadsheets that Xilinx supplies and ensure that you have not inadvertently connected an output to an input-only pin. Most pins are named IOxxx-, and the input-only pins follow the same convention except that they are labeled Ixxxx-.

For our first Spartan-3AN design, being long time users of Xilinx FPGAs back to the XC3000-series, we/I didn't see/notice that some of our output signals were tied to pins short one letter. Fortunately, we/I generally put in a logic analyzer port in most designs, so we used green Kynar wire to mask the error until the design could be properly corrected.

BTW. On the matter of 4-layer PCBs, give Billy Chan at ImagePro in Burnaby, BC, Canada an opportunity on the next go around. My company has been using their service(, and that of Imagineering in Chicago, IL,) for 16+ years. They may be able to provide you a quote for this board at a price that may make it attractive to use multi-layer construction.

Disclaimer - not in business with him, quality may vary, yada yada.

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Michael A.