Concept & Design of 3.3V Parallel 16-bit VGA Boards

[ElEctric_EyE]

Arlet wrote:

ElEctric_EyE wrote:

Why would you want to do this? or maybe which signals would you want to look at in particular? I could surely put in some holes to accomodate the test points, however there are only 3 holes left in v1.0h design.

To make it easier to put a scope probe on a signal, and keeping your hands free at the same time. Holding a probe stable on a 0.5 mm pitch pin while fiddling with the knobs, or a second probe isn't very easy...

Ah, to let you in on a secret, all of the smallest (.008" I.D./.026" O.D.) vias on the board can snugly fit a stripped .010" WW wire into them even without soldering. While they are not guaranteed to be free of solder, looking at all 3 boards, not one of the vias is filled in.

A CLOSEUP shows you the possibilities. v1.0h is virtually identical...

[ElEctric_EyE]

ElEctric_EyE wrote:

A CLOSEUP shows you the possibilities. v1.0h is virtually identical...

Got some neato graphic designs on there too, heh. Will put the order in tomorrow.

[ElEctric_EyE]

I hate that feeling right after I put in the order, and I realize I forgot to do 'such and such'. Well, I don't have that feeling this time around. I will order in 1 hr if I can't make another correction or add anything else. So what if it's potato soup for a week or 2!

[ElEctric_EyE]

Order placed. ETA 3 days.

Used to be 3 days, now it's 5. Email says ETA is 10/18...

[ElEctric_EyE]

Received the v1.0h boards today, 1 day ahead of schedule from ExpressPCB!
Already I have a v1.0i in the works, although changes are purely cosmetic to the graphics at this point. Version 'i' should be the last, I think. I expect Arlet maybe will have some comments for possible improvements to add for the next PVB board run. We shall see his soldering skills!

[Arlet]

ElEctric_EyE wrote:

Received the v1.0h boards today, 1 day ahead of schedule from ExpressPCB!
Already I have a v1.0i in the works, although changes are purely cosmetic to the graphics at this point. Version 'i' should be the last, I think. I expect Arlet maybe will have some comments for possible improvements to add for the next PVB board run. We shall see his soldering skills!

Do you have schematics, by the way ?

[ElEctric_EyE]

Arlet wrote:

...Do you have schematics, by the way ?

No schematics, I find them to be a hamper. I rely solely on the board layout from the beginning of the design. This way there is no possibility of translation errors from schematic to board layout (also I didn't have room for labelling cap's on the board since they're so close together). The layout IS the schematic. I have made an effort to label resistors as they are usually unique values.... Thinking, there are some unique capacitors near the videoDAC. I will post an update for construction.

[Arlet]

ElEctric_EyE wrote:

No schematics, I find them to be a hamper. I rely solely on the board layout from the beginning of the design.

I guess that works well when you can highlight traces on the screen and see the pin numbers, but I find it quite strenuous to try to follow the red/green lines through all the vias on the JPG, and count the pin numbers of the TQFP-100. Luckily, most of the important stuff is documented by the UCF file.

[ElEctric_EyE]

Arlet wrote:

..Luckily, most of the important stuff is documented by the UCF file.

Yes, the .UCF file is key, also the parts list. I've taken pains to keep everything updated. Schematics are a pain nowadays and would slow my progress.

Some tips, in no particular order (parts are highlighted in white):
In regards to the:
(U2) SyncRAM: 2 0603 bypass cap's fit on each power pin on the bottom of the board.

(U5 & U6) FPGA PROMs: 4 0603 bypass cap's on the top.

(U12) 100MHz Oscillator: 2 0603 cap's on the bottom.

(3.3V & 5.0V mains): 2 1210 cap's, 4 0603 cap's on the bottom.

(U1): 7 0603 bypass cap's on top.

(U1): 14 0603 bypass cap's on bottom. 2 1210 bypass cap's on bottom center.

(U3): 1 0603 .1uF

(U3): 1 0603 1uF

Now in retro, would've been easier for schematics, sorry.

Pics are from v.0i, but everything is the same here. My mistake.

[GARTHWILSON]

I think a full schematic is a waste of time in many cases, but you can certainly have schematics of isolated portions, or sumarize certain portions with wiring lists (in text) that are quicker to generate and easier to read than a schematic might be. Laying out a large circuit's schematic in a way that's clear and easy to follow is no small task.

[Arlet]

GARTHWILSON wrote:

I think a full schematic is a waste of time in many cases, but you can certainly have schematics of isolated portions, or sumarize certain portions with wiring lists (in text) that are quicker to generate and easier to read than a schematic might be. Laying out a large circuit's schematic in a way that's clear and easy to follow is no small task.

I agree that laying out all the connections is a pointless exercise. If the memory's A0 is connected to the CPU A0, all you need is a label. So, my preferred schematic is just a bunch of rectangles for each of the chips, mostly with labeled signal wires in logical groupings rather than ordered by pin number, and a few drawn lines that connect individual gates, or analog parts.

[ElEctric_EyE]

Today I was looking to order some 2MBx18 synchronous RAMs for the new supplier I found, GSI Technology. Earlier, I was looking at their 4MBx18 devices. As I was not quite ready to spend $160 for each IC, I looked at their 2MBx18 selection and I could not believe what I found! 4ns speed for Flow-Through mode. Also, these IC's have a pin to select Pipeline (2.5ns speed) or Flow-Through mode. Unfortunately, will have to wait 8 weeks for new stock.

[Arlet]

What clock frequency are you planning to use in your design, and how comfortable are you that it's actually going to work ?

[ElEctric_EyE]

For the PVBs I would like a minimum resolution of 640x480, with a clock frequency of ~25MHz. With a 2MBx16 RAM that's enough for 6 frame buffers and the relatively low clock speed would allow for a possible cpu. I would also like a maximum resolution of 1920x1080, allowing 1 frame buffer. The speeds for this would be approaching 200MHz. I am unsure if anything designed in the FPGA would work at this speed. But since this higher speed part is only $10 more than the pin equivalent 2MB 6.5ns Cypress part, it is a wise decision to use it to expand the possibilities. Picture quality at 1280x1024 is very good running at 108MHz with my current modified 1.0g board and the 2MBx16 Cypress part.

EDIT: I think it's a good idea at this point to keep a record of PVB versions at the head post. I just realized the GSI 2MB part is not pin for pin compatible with the slower Cypress part. So v1.0i will be made to accommodate the faster part. That update still has to be made.

[Arlet]

I got the components (except for the SRAM), and I mounted some on the board. I now have FPGA + PROM installed, plus the regulators, and the oscillator. JTAG shows both PROMs, and the FPGA, and I made a simple test project to toggle some pins, which worked as expected. I have the DAC ready, but haven't installed it yet.

Now, I need to figure out how I'm going to test the VGA. I only have one monitor, and it's hooked up to my desktop PC. I don't feel like disconnecting the VGA connector from the PC every time I want to test the FPGA board.

By the way, I see R10 and R11 marked on the bottom, but the two pads are connected to each other. What's the purpose of these resistors ?