Nice documentation! This should fit in that contraption that i am planing to build!
As for the MC6875 i think it arrived, ill go to the post office tomorrow to pick it up. Ill try to make some changes in my design, hopefully it will fit in the 72'. I won't start building any project until the end of summer, so for now ill stick with code.

Today i got the MC6875L, and i tested it. It works fine when the input frequency is 8MHz (2MHz out), but weird stuff starts to happen after 10MHz (2.5MHz out), the output frequency doesn't increase, but it sticks @2.5MHz, and variates just a bit, i tried 14 and 16MHz, but it just sticks around 2.5MHz at the output? The ic looks new, and i had to bend the pins(like every new ic) to fit it in the breadbord, datecode dates it to the 82', and it gets kinda hot...

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I already ready it before i posted, and either the answer is not there, or i missed it...

Take a closer look at the AC characteristics and the block diagram. The answer is in there.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I took a look at the datasheet again, but i didn't find the answer, i guess i should calculate a bit the values.
But i rigged it up again, but this time i tested the 4x and 2x output, and i noticed that when i pass 10MHz 2x out starts jumping clocks due to unstable clock signal. I shortened the breadbord wires, added decoupling caps close to the chips, and i got a bit better signal. After some more tweaking i got it running at 4MHz, but the output signals (phi 1 and 2) are not exactly ideal... And it gets very hot...

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Well, it gets very hot only on with the 16MHz clock, while on 8MHz, its only kinda warm...
It is not damaged, it works fine at 4 and 8MHz, outputs phi 1 and 2 don't overlap.

I also noted the bus phi2 pin, which is the phi1 inverted, so what is the trick with it?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Well, the chip has the phi1 and phi2 out for the cpu, but it also has a separate phi2 out called bus phi2, which is phi1 inverted, and it is wider(lasts longer) than the regular phi2 out.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Ill avoid it then, and use the regular phi1 and phi2 out for now.

Dajgoro:

Be careful with using phi1 and phi2 to drive anything but CMOS loads (two MC6800 MPU loads is all that is indicated). The data sheet clearly shows that those two signals are CMOS outputs with a drive strength of +/- 200 uA. On the other hand, Bus phi2 is a TTL-compatible output and can source 10 mA, and sink 48 mA.

On the previous issue, I think BDD wanted you to notice that the minimum period specified was 500 ns (2 MHz), and that the block diagram showed that none of the FFs where edge-triggered except the reset and memory inputs. I generally take those types of block diagrams to indicate that the circuits are more analog than digital (in the modern sense). This means that internal delays in the differential switching circuits are used to cause the latching/FF actions. Much like using a cross-connected NOR/NAND to make a latch, care must be taken to ensure that the signal transitions and the internal circuit delays are appropriate for the operating speed.

Also, I think BDD wanted you to look at how much time the signals take to transition from one state to another. It is during the transition, the time when both transistors in the CMOS totem-pole output are changing from on to off (or vice-versa) that they are in a linear operating region. During this time is when they dissipate power. When fully on or fully off, the enhancement mode FETs in this device do not dissipate any significant power. The off transistor does not because there is very littly current flowing in the channel, and the on transistor does not because the channel resistance is low.

When I looked jump to the link and looked at the block diagram as BDD indicated, I took it to mean: beyond this point there be dragons. Doesn't mean that you can't push the device, but as you've experienced, it may behave very differently than the data sheet specifies.

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Michael A.

Dajgoro:

Posted on GitHUB the completed code for the Serial PCU and its incomplete testbench.

Like the Serial ALU, the Serial PCU fits into a XC9572-7PC44. Will be completing the Serial PCU testbench and completing that verification in the next few days. I had updated the documentation with design information regarding the Serial PCU, but I have not uploaded it since during the actual implementation of the Serial PCU I determined that my original concepts would not perform correctly.

Therefore, the header of the Serial PCU source file represents the best available documentation on that component. Some advance information regarding the next component, the MiniCPU-S Execution Unit, is available in the header of the Serial PCU and in the comments associated with the testbench tasks used for Serial PCU testing.

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Michael A.