Beginners CPLD
Re: Beginners CPLD
Quick question. When i assign a logic value to a pin, or when i connect two output pins together(one pin is in, one out), is it necessary to use a macrocell, or can the interconnecting matrix handle this?
Re: Beginners CPLD
The port list at the top of your project hierarchy will define the pins, and whether they are input, output, or bidirectional. What I have noticed is the input pins do not require a macrocell, and the CPLDs routing matrix generally allows an input pin to be placed on any pin of the device. Any outputs from a FF or a combinatorial output will require a macrocell.
I would recommend that you do not try to specify the placement of the pins on your CPLDs until after most of the design has been entered, synthesized, and fitted. The fitter will generally place the pins as required by the underlying structure of your project. The problem that I found with the serial ALU design that I sent you a link for earlier was that, for most of the registers, the number of p-terms required was fairly low. However, at the MSB and LSB ends of the shift registers, the multiplexers required to implement the ALU instruction set required a large number of shared p-terms in order to be implement the specification. This means is that the AND gates (p-terms) and parts of the OR gates in adjacent macrocells are used to implement the logic equations.
It is difficult to simultaneously optimize the pin LOCs and the distribution of the macrocells. The equations needed for each register or combinatorial output are best optimzed by the fitter. What I found with the serial ALU is that the p-term collapsing limit affects how the fitter breaks down the synthesizer's equations. That parameter limits the number of p-terms that may be chained together using the p-term sharing logic from adjacent macrocells in the function block. The result is that additional macrocells may be used, and their local feedback into the signal routing matrix, with a marginal increase in the signal delay, is used to route that partial logic function to the macrocell which requires more that its 5 independent p-terms.
The other parameter that affected the fitter was the input collapsing limit. I also had to decrease that value in order to allow the fitter to use the signal routing matrix to route the macrocell feedback signals to the macrocell needing that term. The end result of these changes is that complex logic equations required for a single FF or output need to be heuristically distributed by the fitter across the chip. In most instances, reviewing the placement of the serial ALU's equations makes some general sense, but in some isolated cases, the equations are distributed to other function blocks. The only explanation is that the logic function needed to be separated from others in its logic group in order to find a place where sufficient p-terms and input resources existed. (Sometimes it is just due to the random seed used to aid these types of algorithms.)
Locking down the inputs may not be a particular hindrance except that decreasing the input collapsing limit may mean that a necessary input, locked to some pin with direct connection to another function block, may not be routable to a function block where it is also needed. The boolean reduction of complex logic equations is difficult for a human when it's just four or five terms, but when 10-30 external and internal signals enter into the mix, it is virtually impossible.
That is not to say that you shouldn't try and make the problem easier for the fitter. For example, I always try and define state transitions in a gray coded manner, or in the case of the serial ALU, to define related instructions such that any fitting algorithm should be able to optimize out one, two, or more of the inputs because they are logically adjacent from a Karnaugh map perspective.
There is a limit to how much help you can give the fitter because most people can't perform the logic reductions in their heads. However, there is no reason for you to not do a little advance planning.
I would recommend that you do not try to specify the placement of the pins on your CPLDs until after most of the design has been entered, synthesized, and fitted. The fitter will generally place the pins as required by the underlying structure of your project. The problem that I found with the serial ALU design that I sent you a link for earlier was that, for most of the registers, the number of p-terms required was fairly low. However, at the MSB and LSB ends of the shift registers, the multiplexers required to implement the ALU instruction set required a large number of shared p-terms in order to be implement the specification. This means is that the AND gates (p-terms) and parts of the OR gates in adjacent macrocells are used to implement the logic equations.
It is difficult to simultaneously optimize the pin LOCs and the distribution of the macrocells. The equations needed for each register or combinatorial output are best optimzed by the fitter. What I found with the serial ALU is that the p-term collapsing limit affects how the fitter breaks down the synthesizer's equations. That parameter limits the number of p-terms that may be chained together using the p-term sharing logic from adjacent macrocells in the function block. The result is that additional macrocells may be used, and their local feedback into the signal routing matrix, with a marginal increase in the signal delay, is used to route that partial logic function to the macrocell which requires more that its 5 independent p-terms.
The other parameter that affected the fitter was the input collapsing limit. I also had to decrease that value in order to allow the fitter to use the signal routing matrix to route the macrocell feedback signals to the macrocell needing that term. The end result of these changes is that complex logic equations required for a single FF or output need to be heuristically distributed by the fitter across the chip. In most instances, reviewing the placement of the serial ALU's equations makes some general sense, but in some isolated cases, the equations are distributed to other function blocks. The only explanation is that the logic function needed to be separated from others in its logic group in order to find a place where sufficient p-terms and input resources existed. (Sometimes it is just due to the random seed used to aid these types of algorithms.)
Locking down the inputs may not be a particular hindrance except that decreasing the input collapsing limit may mean that a necessary input, locked to some pin with direct connection to another function block, may not be routable to a function block where it is also needed. The boolean reduction of complex logic equations is difficult for a human when it's just four or five terms, but when 10-30 external and internal signals enter into the mix, it is virtually impossible.
That is not to say that you shouldn't try and make the problem easier for the fitter. For example, I always try and define state transitions in a gray coded manner, or in the case of the serial ALU, to define related instructions such that any fitting algorithm should be able to optimize out one, two, or more of the inputs because they are logically adjacent from a Karnaugh map perspective.
There is a limit to how much help you can give the fitter because most people can't perform the logic reductions in their heads. However, there is no reason for you to not do a little advance planning.
Michael A.