Beginners CPLD

[Dajgoro]

I found a project for the xc9536, and i tried to see if the jtag works, and guess what... I checked everything 3 times, power, jtag connector, i even took the jtag apart, and tested the voltages on the ic and surroundings, its all like what it should. When i look with the socpe, i can see data going in and out at 5V levels. Verify, program, and similar stuff fail, but erase works.
I tried replacing the cpld, but nothing changed. And still no clues for what is wrong with my project...

[MichaelM]

I recently had to resurrect an old installation of ISE8.2i to make some corrections to an old CPLD. It is a daunting issue to download and install one of these older tools, but I've found that support for some of the legacy components is not at all up to par on the latest releases.

Just something to consider.

[Dajgoro]

Where can i find the ISE8.2i?

[Nightmaretony]

back on CPLDs. Board made, external connectoring slightly different. Already made the pin map. Logic be next in the shindig. Wlll have questions along the way, especially in 2 fun parts in the design. bank switching and an io overlay.... (the io occupies the first 256 bytes of the eprom space at $8000. You stick a value in a certain location and read the data from the eprom in another. This allows reading revision and checksum data....





http://www.nightmarepark.com/6502/Pinba ... tuffed.jpg

[MichaelM]

You can find ISE8.2i on the Xilinx website. It's generally now located in a legacy tools directory. If I recall, you have to register for a key, but it should be at no cost.

[Dajgoro]

I downloaded ISE8.2i but now its asking me an registration id witch seems to be discontinued, what now, how did you install it.
As for that working example that i downloaded, its not working anymore, it throws the same errors as in my projects...

[MichaelM]

On that same website there is a place on the downloads page where you can register for an ID. For legacy products like ISE8.2i, it should be be free and a simple matter of agreeing the the terms of use. Create an account if you don't have one, and select WebPack. For the CPLDs that you are using, that should be sufficient. It should also provide support for the Spartan-II, SpartanXL, and the low end Virtex 5V FPGAs, and the predecessors to the 3.3V Coolrunner CPLDs.

[Dajgoro]

ISE 10 won't work either. It offers me only FB1 and FB2 pins, and it can't fit it no matter what i try...

[ElEctric_EyE]

Dajgoro wrote:

...and it can't fit it no matter what i try...

You might want to look at xapp444.

[Dajgoro]

For test i am just trying to implement and AND gate.
It won't work with 8.1 either, i am starting to think i am doing something wrong...

Here is th ucf file:

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NET "AIN1"  LOC = "A1"  ;
NET "AIN2"  LOC = "A2"  ;
NET "AOUT1"  LOC = "C6"  ;

And i get:

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ERROR:Cpld:832 - 'AOUT1' is assigned to an invalid location ('C6') for this
ERROR:Cpld:832 - 'AIN1' is assigned to an invalid location ('A1') for this
ERROR:Cpld:832 - 'AIN2' is assigned to an invalid location ('A2') for this
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with

[ElEctric_EyE]

It looks like your LOC assignments in your .ucf file have incorrect syntax. You will have to look at your CPLD datasheet and determine which pins you would like your "A1", "A2" "C6", etc. signals to be assigned to. Here is a proper syntax, I've seen Arlet do multiple pin assignments somewhere, easier to type in than my post here. I'll post it, if I find it...

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NET "DataBusOut(7)" LOC = P83;	//for TFT
NET "DataBusOut(6)" LOC = P82;	//for TFT
NET "DataBusOut(5)" LOC = P81;	//for TFT
NET "DataBusOut(4)" LOC = P80;	//for TFT
NET "DataBusOut(3)" LOC = P79;	//for TFT
...

These pin assignments were for a Spartan 6.

[Dajgoro]

I've checked the pins in the datasheet. In the last example i entered random pins, but for example, the datasheet specifies B1,B2,A3 as part of funcion block 1, and when i rerun all, the error keeps coming:

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ERROR:Cpld:832 - 'AOUT1' is assigned to an invalid location ('A3') for this
ERROR:Cpld:832 - 'AIN1' is assigned to an invalid location ('B1') for this
ERROR:Cpld:832 - 'AIN2' is assigned to an invalid location ('B2') for this
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with

When i run pace, it offers me FB1 and FB2 under the loc column, shouldn't there be listed the pins?

On my college lab, i worked with the spartan 3 development board, and i had no such problems there of this kind.


In 10.1 the project that i downloaded fits successfully, and it even recognizes that the jtag is connected to the cpld, wee!

[Dajgoro]

It seems that the xc9536 likes the pins assigned literally, the thing with the letters and number like I've seen like in a example, doesn't work. Here is the ucf that worked:

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NET "AIN1"  LOC = "P3"  ;
NET "AIN2"  LOC = "P4"  ;
NET "AHI"  LOC = "P6"  ;
NET "AOUT1"  LOC = "P5"  ;

And i got a functional AND gate, with pin 6 being stuck to hi.

[MichaelM]

Dajgoro:

Perhaps I'm off track here, but I think EEye's correct about your ucf file syntax. You appear to be using a pin label syntax I've come to expect from BGA packages, not the TQFP or PLCC packages that I expect you to have purchased.

I have been working this weekend toward that CPLD minimal CPU implementation we discussed earlier in the week. The ALU portion is synthesizing and fitting into 27 macrocells. I got to this point using my 10.1i SP3 toolset without setting any constraints. Seeing yours and EEyE's posts, I went into the tool and had it generate the ucf for the pins it chose to see the syntax. The following is a snippet from the ucf file produced by ISE 10.1 for a XC9572-7PC84 CPLD.

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#PINLOCK_BEGIN

#Sun Jul 29 19:34:48 2012

NET "CE"             LOC =  "S:PIN70";
NET "Clk"            LOC =  "S:PIN9";

In the case of these pin locks, I see the syntax I would expect from a PLCC-84 package. In other words, I see a Pxx or Pinxx instead of a Ax syntax.

I haven't used CPLDs in a long time. FPGAs have been much more applicable to my projects, and the decoding functions I used to use them for have essentially been built into the microprocessors that I've been applying. It is curious to note a special option available for the part type: XC95*, which essentially allows the tool to select the CPLD into which the design fits. I'll see how that setting affects the fitting of a minimal CPU into a CPLD.

Seeing how the ALU adder expanded my estimate for the ALU's adder/subtractor, I am going to predict that the minimal CPU will likely overflow the XC9572, and may require a 108 macrocell (as suggested by Andre Fachat) or even the larger 144 macrocell device. Earlier today, I found WP214, "The TTL Burn-Rate of Xilinx CPLDs", on the Xilinx website. It provides some interesting estimates for the macrocell requirements of standard TTL MSI components/functions.

When I have completed a minimal CPU in an XC95xxx component, and gotten a functional testbench running for, I'll post it to github and send you a link.

As I said above, the ALU portion is coded and synthesizing, and I'm currently designing the control logic and execution state machine. I've defined an instruction set based on some of my current FPGA work. I'll wait until it's complete before claiming success, but given the synthesis and fitting results for the ALU logic, there's a good chance of that for the instruction set and CPU architecture I've defined.

[ElEctric_EyE]

ElEctric_EyE wrote:

...I've seen Arlet do multiple pin assignments somewhere, easier to type in than my post here. I'll post it, if I find it...

Just so I don't confuse anyone, I was mistaken about my comment about multiple pin assignments. I meant multiple values could be assigned to each pin, as shown below. I believe that this applies to Xilinx FPGA's only. So sorry, I didn't mean to add confusion to this CPLD discussion. It is proper syntax though.

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NET "SCL" LOC = P88 | IOSTANDARD = LVCMOS33;
NET "SDA" LOC = P87 | IOSTANDARD = LVCMOS33;