6502-Core Comparisons: Fitting a Xilinx Spartan 2 XC2S200

Topics relating to PALs, CPLDs, FPGAs, and other PLDs used for the support or creation of 65-family processors, both hardware and HDL.
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Arlet
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Post by Arlet »

BigEd wrote:
In more concrete news, I tried to fit Arlet's core (the smallest) to CoolrunnerII, and it failed to fit the largest CPLD: 577 macrocells needed versus 512 available. Not missing by an enormous margin, but missing.
I assume you tried the old core without BCD support. Correct ?

Ah, I see you already said that you tried the smallest. Never mind.
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BigEd
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Post by BigEd »

ah, actually no, I merely meant that yours is the smallest of the collection of cores. We can indeed lose a bit with BCD and a bit by losing RDY. (But not much.)
ElEctric_EyE
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Post by ElEctric_EyE »

If I may interject, I thought I was able to fit one of the cores (I thought it was Arlet's) into a Xilinx 208-pin CPLD...

I searched this forum, but could not find the post I'm referring to. But I would've sworn that I'd posted it somewhere on this forum.
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BigEd
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Post by BigEd »

Just checked - looks like the largest CPLDs are very expensive (£40, and that's only 384 macrocells). So if the advantage is the 5v tolerance, it would have to be very important. (Smaller CPLDs are a different matter, but for a super fast 6502 part it seems to me that a small Spartan 3AN at £7 makes more sense.)
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BigEd
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Post by BigEd »

I see Oleg Odintsov has posted a new core:
http://opencores.org/project,ag_6502
It's unusual in being phase accurate, a relatively compact implementation but coded in some High level source compiled to verilog.
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BigEd
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Post by BigEd »

Also Ian Chapman posted a core back in late 2010
http://opencores.org/project,lattice6502
which is not intended to be cycle accurate but to take fewest clock cycles per instruction.

From the source:
---- I will make it run as fast as I can. Timing not per a real 6502.
---- Lattice EBI has clocked address inputs, so as not to add a cycle
---- 6502 address outputs are not latched. The data output of the EBI ROM and
---- RAM is not clocked.
---- To maintain speed the 6502 address to ROM/RAM is not clocked and the data
---- returned is not clocked by ROM/RAM. Structures of form address <= address + "1";
---- cause a race condition. I had to store the address from the mux for
---- INC type instructions ie read then write.
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Re: 6502-Core Comparisons: Fitting a Xilinx Spartan 2 XC2S20

Post by fachat »

I think you finally may add the 65k core to the list of available cores :-)

http://www.6502.org/users/andre/65k/index.html

André
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/
ElEctric_EyE
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Re: 6502-Core Comparisons: Fitting a Xilinx Spartan 2 XC2S20

Post by ElEctric_EyE »

So it is a fully functional 6502 core as well? I can add it in a couple days. Thanks!
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Re: 6502-Core Comparisons: Fitting a Xilinx Spartan 2 XC2S20

Post by fachat »

ElEctric_EyE wrote:
So it is a fully functional 6502 core as well? I can add it in a couple days. Thanks!
It's binary compatible, but of course adds my extensions. It's huge though - extensions were more of a goal than code/silicon size.
Still kind of alpha though.

André
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/
Oleg Odintsov
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Post by Oleg Odintsov »

BigEd wrote:
I see Oleg Odintsov has posted a new core:
http://opencores.org/project,ag_6502
It's unusual in being phase accurate, a relatively compact implementation but coded in some High level source compiled to verilog.
Hello everyone! At present, I am testing my new core and preparing documentation for both compiler and core. So if you found some mistakes or improper behaviour of the core, please send me a bug report.

Latest version of the core stably works at 10 MHz (using 50 MHz clock source for phase shift and delays). I was trying to increase it's speed by using DCM to multiply clock source to 200 MHz thus enabling to increase cpu speed to 40 MHz, but it doesn't works in my Spartan 3E (even if I was using 1 MHz clock source with 200 MHz phase shift). Did anybody happened to do this on Spartan family of FPGA?
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BigEd
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Re: 6502-Core Comparisons: Fitting a Xilinx Spartan 2 XC2S20

Post by BigEd »

Welcome Oleg!
I can't answer your question, but I'm sure someone can.
This is presumably your system: http://www.youtube.com/watch?v=rOFKD8A-syU
Cheers
Ed
Oleg Odintsov
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Re: 6502-Core Comparisons: Fitting a Xilinx Spartan 2 XC2S20

Post by Oleg Odintsov »

BigEd wrote:
Welcome Oleg!
This is presumably your system: http://www.youtube.com/watch?v=rOFKD8A-syU
Yes, those videos tagged with "agat-7" are mine.
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Re: 6502-Core Comparisons: Fitting a Xilinx Spartan 2 XC2S20

Post by ElEctric_EyE »

Oleg, welcome to the Forum!
Another one bitten by the 6502 'speed bug' :D
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Re: 6502-Core Comparisons: Fitting a Xilinx Spartan 2 XC2S20

Post by ElEctric_EyE »

Rob Finch has a new website. I will update the link in the original post.... Thanks for Dr. Jeff alerting me. I see Rob has contributed to 6502.org's sister site. Welcome back!

I'm thinking of re-doing this thread but doing the comparisons around a Spartan 6 device, since we have some new additions like Oleg and MichaelM's softcore. I know I've said it before, but tomorrow I will start on the new thread, with pics as attachments. Hopefully 6502.org Admin will not have a problem with this. The service Photobucket, which I used to use has changed too much to be useful.
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Re: 6502-Core Comparisons: Fitting a Xilinx Spartan 2 XC2S20

Post by ElEctric_EyE »

Also, Mike J. has a recent update on his fpgaarcade site just this month, after almost a year delay.
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