I'm busy revising my TTL6502 project, http://www.baltissen.org/newhtm/ttl6502.htm. The original idea was to build a 6502 only TTL ICs. But I soon found out that that was undoable from a practical point of view: the Instruction decoder and the ALU were the trouble makers. So I decided to cheat a bit and to use FlashRAMs.
To handle 8-bit operations I would need a FlashRAM with at least 24 inputs. Not having them I decided to cascade two, each handling four bits. But that idea comes with a penalty: the access time of the ALU is 140 ns. This means I can only emulate the 6502 up to 3 MHz.
During the revision I thought about expanding the 6502 a bit with, for example, 16-bits registers. Only after weeks I realised that I needed a 16-bits ALU as well. Using FlashRAMs means a 280 ns. access time, meaning I can forget 2 MHz operations
My question: has anybody a better idea?
Many thanks in advance!

