Hi Grant
impressive breadboard!

Couple of things: as you say, the edge rates seem to be the major determining factor, rather than the absolute clock speed. (Is there ever any advantage in adding load to signals?? The BBC has series resistors on the DRAM strobes but I assume they are to add delay.) Good tip on logic family choice.

But secondly, would it be true that a 10MHz z80 design would only be clocking the bus at about 5MHz? (I've got an interest in this because of my query elsewhere about preferred processors in chess machines.)

Here's my simplistic model, if circuits are synchronous:

For clock lines, and clock-like lines such as RAM strobes, it's crucial that no noise or ringing should be big enough to be interpreted as an edge, and it's crucial that the delays experienced at different endpoints and by different signals are well enough matched that the circuit works. For data lines, it's crucial that signals are settled by the time clocks arrive, and that they are not disturbed by the clocks or by other signals at the time they are sampled.

In both cases, it's crucial that the power rails are clean enough that the level of the signal or clock is not misintepreted by the receiver.

Fast edges are a problem because they are worst case for ringing, for crosstalk and for dragging the power rails.

Cheers
Ed

Hi Ed.
The Z80 uses 4 clock cycles (normally) per Opcode read, but the 2nd two are regarding refresh. So, there is only 1.5 cycles from the memory request becoming active to the CPU grabbing the data for an opcode read, and given the access time delay when reading memory, this doesn't give much time for the data lines to settle. Max speed that I have got is 12MHz. Couldn't go any faster but that may have been down to the CPU (I overclocked it from a 6MHz device!!) and RAM access, so I guess I didn't push the breadboard option to the limit.

...obviously, this is a 6502 forum, not a Z80 forum, but the principles are the same, and I don't have pics of my 6502 circuits (yet)

I haven't tried any DRAMs on breadboard, only SRAM.

I've yet to find the "best" way to route power planes on multiple breadboards, and welcome any suggestions

Regards.

Grant.

That solderless breadboard construction at http://home.micros.users.btopenworld.co ... mClone.JPG is very neatly done. So many .300"-wide ICs! What are they for?


The first (and only) computer I made with a plug-in-type breadboard used 74HC, and after I figured out that the 6522 needed the chip-select select lines valid and stable before φ2 went up, never had any more trouble with it; but it was a lot smaller. I wish I had taken a picture of it. For computer construction though, when we talk about breadboards, it's normally not the plug-in type. Those are the worst of all worlds performancewise. I do use them a lot for low-end analog work though.


Yeah, that doesn't accomplish the purpose of a ground plane.


Planes aren't really "routed" or they wouldn't be planes; but if you mean how to connect the power between boards, just have decoupling where they leave the board, and then focus on ground return integrity for the signals that go from board to board. That means far, far more than just a low-impedance ground connection between them.

Again my first post in this topic, which is the first one after Ed's initial post, has a lot of links to good pages on this stuff, and some of the pages have a lot of additional links. There's too much to give in a paragraph or two, and it has taken me years to really get to my current level of grasp on the subject, even though I worked in GHz+ power amplifiers in the mid-1980's. We are incorporating a class-D (switching) amplifier along with a switching power supply in something we're working on at work now. The other engineer had evaluation modules from the IC manufacturers themselves and was having big trouble with switching noise, so he asked me to lay out the circuit myself. He just gave me the report this morning that it was super quiet. He was extremely pleased.

Unlikely. As Bil Herd of C128 fame explains, the series resistors are to reduce reflections, i.e. to improve signal quality: http://www.6502.org/users/andre/icaphw/design.html

André

I'll gladly concede that point!

It is hard not to notice that Garth is strongly promoting 65SIB standard and stigmatizing the CPU bus lines going off the board as a "newbie technique". I have seen it in few threads, including one I started yesterday. I just want to add few remarks regarding this subject. It is not that unusual to run CPU bus off the board or have microcomputer system organized around such a bus on a passive back plain with extension sockets. It is certainly not a newbie thing to do. Once you are aware of speed limitations of such architecture, it is quite OK to use it. It is part of the design process. Classic example of such architecture is S-100 bus used in Altair 8800 system. With such architecture, designer must determine if the bus is to be high-load (many expansion slots, many ICs) or not. With high-load bus on the modular system (more than 10 IC inputs per bus signal, more than 20 ICs total), each expansion card should provide its own buffering of the bus signals, address and data lines etc. and these sets of buffers impose great speed penalty (each adds additional signal delay, because between CPU board, buffered as well, and extension board is always at least 2 sets of buffers). Rule of thumb for such architecture is that they are "safe" for bus clock speeds up to 2 MHz. However such design allows to build big microprocessor systems with many modules attached to them. If designed system is to be smaller, have up to 20 ICs (say up to 10 IC inputs per bus signal), it is good enough to create non-buffered CPU bus for fast peripherals (RAM, ROM, NMOS, CMOS) and buffered I/O bus for slower peripherals, with just one set of buffering ICs between CPU bus and I/O bus. It is a classic design, not a "newbie error". These were valid design techniques in the 70s and 80s. I agree that with modern electronics such designs are rendered obsolete. Unless it is your intention to build an obsolete system using obsolete chips. Which is what I am doing.

With best regards...

_________________
Marek Karcz
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"Don't worry. We've got our best people working on it."

I'll try to restate that as pros and cons - I think there are good points there - but I don't like to see it looking like attack and defence.

old-fashioned modular design with extended system bus

- good for historical re-enactment, using low-integration chips
- solid at low speed
- needs buffering if the load is high relative to the available drive
- allows for many modules in the buffered case
- is possible to mix unbuffered fast cards (memory) and a buffered slow bus (i/o)
- will need to pay attention to cross-talk and sheilding, to some extent

serial interface bus is a more modern idea

- fewer wires
- fewer concerns about crosstalk and skew
- daisychaining allows for almost unconstrained expansion
- based on standard serial protocol supported by standard chips

Hope this helps.
Ed

Very well put, Ed. It's not our intention to make anyone do things a certain way, but we do enjoy helping and learning. Newbies unwittingly do many things the hard way, with poor ROI. We all start there. I wish this forum existed in my early years. My first home-made computer, modeled partly after industrial card cages of the day, was an awful lot of work, and in spite of my dreams, didn't really do anything useful. However one benefit we didn't have back then is all the SPI and I²C ICs we enjoy today which keep project size much more manageable because there are so few connections to make. Without them, my ideas for my next computer proved too grandiose to ever finish. 65SIB is basically an SPI extension intended to facilitate off-board expansion with multiple devices ranging from very dumb to very intelligent, and part of the idea was that we could share designs and even hardware. I have been a little disappointed with how much work it is to hand-wire the connectors for the daisychaining (I might get tiny PC boards made for the job), but that's no reason not to use SPI or I²C which give you a simpler, smaller, more modular computer with nearly unlimited I/O.

Some members will be happy to start at 2MHz or less, and using a 2MHz processor's own buses out on the backplane, whether buffered or not, will be fine. This particular thread however is intentionally for how to achieve the highest possible speeds we can with limited non-professional resources.

Incidentally, the output-pin drivers of the CMOS 6502 and peripheral ICs is very strong-- far stronger than the old NMOS 6502. Couple that with all-CMOS loads (there's no reason to use 74LS anymore), and there's no need to add the bus buffers. WDC's 65c22 (I've measured it) can even pull up to a logic high with 40mA, which is 100 times as strong as the NMOS specification.

Only pros were listed...

...but I have some con:

- cumbersome and not straightforward programming of serial protocol with significant overhead.

I think no serial protocol is able to replace or outdo fast parallel bus. Remember complaints of Commodore 1541 drive users? It used basically a serial equivalent of SCSI bus, with up to 8 addressable devices on the wire. Sloooow. There is a reason why graphic adapters in modern computers are put on fast parallel bus close to CPU while USB is used for relatively slow I/O devices. If you need to move huge amount of data fast, you need multiple wires to handle bytes, words etc. at a time. I agree to the above pros though, it is true for small multipurpose/automation microprocessor systems. Less wires is good in this case. Thank you for that comparison.

_________________
Marek Karcz
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"Don't worry. We've got our best people working on it."

Surprisingly, in high-performance digital equipment, serial is actually faster than parallel, which I understand to be because you can have improved transmission lines and not have the skew problems with different bits of a parallel interface arriving at different times.

IDE (parallel, with ribbon cables) maxed out at 130MB/second. It got replaced in 2003 with serial ATA which maxes out at 600MB/second (version 3.0, 6 gigabits per second), over four times as fast as IDE, including the protocol overhead. That's 100,000 times as fast as a 56K modem from just a few years ago. The C64's serial IEEE-488 implementation disc-drive interface design was purposely slowed down for a reason I don't remember at the moment (it seems like it was for something they ended up never implementing), but it did not run as fast as a 1MHz C64 could have done it.

SPI maxes out at 50-100Mbits per second, or around 5-10 MBytes per second. A 20MHz 65816 with its block-move instructions goes less than half that fast. When you take video with your digital camera, the data is recorded on the SD card in serial, in real time. DVDs of course give the digital video data in serial.

Daryl (8BIT here on the forum) offers his 65SPI chip which is a 65-bus-compatible I/O IC that can run with a 14MHz 6502 or 65816, and takes care of the shifting and so on, shifting at a rate up to half the φ2 rate, meaning up to 7Mbits/second, if the computer can handle the data fast enough.

Admittedly, for our applications, serial will be slower; but many of them, like UARTs, keypads, digital thermometers, digital pot.s, relay drivers, DMMs, flash memories, small LCDs--the list is endless--have pretty mild speed requirements. Only a few of the very fastest things need to go on the main computer board, on the processor's own buses. I have my A/D and D/A converters on 65c22 parallel ports for maximum speed. Writing to the D/A is just STA $5001. Reading the A/D requires five machine-language instructions (including a NOP for timing). Unfortunately it's not fast enough to put it directly on the bus and read it like a memory location.

If you don't use Daryl's chip above, and you bit-bang instead, bit-banging both SPI and I²C is very simple. It does not require any precise timings like RS-232 does, and once you've written the simple basic routines or macros, you can re-use them for interfacing to all the other ICs with the same interface. I like to put the SPI clock bit on a bit 0 of a port, so to make it go up and back down for example only requires INC, DEC, two ML instructions, without affecting A, X, or Y. I like to put input data bits on bit 6 or bit 7 so you can use the BIT instruction and then immediately branch on the N or V flag without ANDing, and again without affecting A, X, or Y.

For some things, you can use the 6522's shift register, which can shift data in and out just about as fast as your program can handle the data, so in that case there's no real speed penalty at all. Edit: And! All of that can go faster with the faster clock speeds afforded by keeping the processor's own buses from going off the board.

A very valid points there. Thanks Garth!

_________________
Marek Karcz
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"Don't worry. We've got our best people working on it."

Just to be fair and provide the whole picture:
SCSI Ultra 640 (parallel interface) provides faster transfer rates than SATA. The cost is higher but justified in some cases (servers and disk arrays). It also allows multiple devices per channel while SATA allows only one unless port multiplier is used.
[After Wikipedia: http://en.wikipedia.org/wiki/Serial_ATA ... ther_buses]

Thanks

_________________
Marek Karcz
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"Don't worry. We've got our best people working on it."

Hm, I would not call it "newbie" - as it was a common technique in those days. I have even used it myself.

However, at least in my experience "just" using newer technologies may break a design where CPU lines go off the board. My self-built computer I built from '89 I used then-standard 'LS technology, and I could run my machine even up to 2MHz quite fine.

These days I am more using 'ALS or 'HCT technology, and the system is getting unstable, suffering from bus reflections that you can see on the 'scope. Even bus terminators did not help in all situations.

And that is even easy to explain. Newer technologies are meant to be used with higher frequencies. So the signal transitions are much faster, leading to much more and higher noise frequencies. Those wreck havoc on an off-board bus. Actually on any bus that is not properly designed and terminated - but off-board buses are much more susceptible for that, as everything depends on board design (how many inputs, what type of inputs), how many boards on the bus, even where you put each board on the bus. Those are the issues I am fighting with the latest boards I designed - so I decided that that'll be it after the one I'm currently working on and use a single-chip computer with separate, (most likely) serial buses for connectivity.

So in those days it was a valid technique, but in my opinion things have changed since then. Just my experience.

André

for my owbn pinball, ti takes data and address busses off the board in an almost identical bus connenctor to the WDC development board bus with the big difference of the busses having buffers involved, 74ls or hc or als245s which I enjoy . Tis a deliberate older fashioned buss gig, but should do the job I need for it...

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"My biggest dream in life? Building black plywood Habitrails"

Yesterday i finally decided that i should make some sort of signal amplifier for phi2 and r/w signals that go to my expansion board. So i took the fastest gate that i had, the 74ls08 (8ns) and i used it as a signal amplifier. The signal looked kinda better with it, and my crtc board worked as usual, but my lcd didn't. First i thought that while i was soldering, i accidentally did something wrong. So i checked everything, but all seemed fine, i also re soldered suspicious connections, but no help. Here and there it would work for a moment, so i was convinced it was a bad connection. Things got weird when i turned on my scope, and found out that when i touch the r/w line the lcd starts working. It seems i made some sort of reflection when i cut the load from the r/w output. I guess i should make some sort of terminator now... Here is a video where i touch the r/w pin with a screwdriver.
http://www.betaic.com/wp-content/uploads/2012/04/rw.mp4(you might need to have some fancy video codec to open this video, since it was recorded with a Windows phone 7)

The link is located on a website that is still under construction, me and my friend were hoping to make some sort of hardware software website for our projects and stuff...