Is there a minimum time that NMI must be idle, e.i. high, before the next edge?

In trying to couple a 3Com 3C509B to my Vic 20 it will work but eventually it seems to miss an NMI interrupt and then stops working (because the interrupt is missed it is never cleared, effectively blocking further interrupts).

I suspect that the NMI returns high for less than 500ns if another interrupt from the card is pending when the previous one is cleared, trouble is it happens too infrequently to see/measure with what I have.

The annoying thing is it works /most/ of the time.

Lee.

Lee,

I do not have a firm answer to your question. I do have a possible "working theory".

The WDC W65C02S docs on the NMI say:

So, for this nesting to work properly, the first NMI must have time to push the PC and SR onto the stack and load the NMI vector into the PC before a second NMI can be processed (7 cycles). Assuming a 1MHZ clock, then 7us is needed in between each NMI.

I wish I had some proper test gear to validate that.

Good luck!

Daryl

I've been browsing the datasheets as well - still no enlightenment.

The problem is not the time metween successive interrupts, that is many 10's of ms but the time between NMI returning high and the next -ve edge.

As each interrupt is generated the NMI routine sets a flag and exits with the NMI line still held low. The main routine sees an interrupt flagged and processes it, once this is done the interrupt is acknowledged by writing to the card which releases the NMI line. If there are any further interrupts pending a new interrupt is generated almost immediately. It's this time which I suspect is too short.

I've tried to test the NMI response using a routine that generates an interrupt repeatedly under software control butthat works all the time. Unfortunately you can't queue the software interupts on the card like it does the FIFO interrupts.

I've had an idea to use a 74LS74 as a resettable external NMI latch, I'll try that tonight.

Cheers,

Lee.

I understand better now. What value of pull-up resistor is used on the NMI line? Purhaps its not rising fast enough for the 6502 to recognize a valid high. The docs recommend 3k ohm. Maybe a lower value (2.2k) will improve the response??

I wish I had access to a scope!!!

Daryl

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Even though NMI is edge triggered, it is probably synchronized internally to the processor clock to avoid metastability issues. Meaning it may need to have a high period of at least one processor clock period in order to be able to recognize another interrupt. (The edge is likely detected using a clocked circuit.) Since the VIC is only running at 1MHz I'd make sure the NMI is high for at least 2 cycles or 2us. Could use some sort of pulse extender.

It's all in the timing diagram: page 20 of the W65C02 datasheet. NMI is sampled on the falling edge of phi2. There's a 10ns setup and 10ns hold time. You'll need to synchronise it yourself.

NMI is not edge triggered in the sense that the hardware is looking for an edge. It's looking for a steady state at particular moments in time. A change in the state triggers the interrupt, not the state itself (as in the level-sensitive IRQ input).

Well much tearing out of hair and gnashing of teeth has gone on.

Rise and fall times were suspect at first but measuring them revealed <20ns rise and 8ns fall, plenty fast enough.

I couldn't think of a way to repeatedly trigger the successive interrupts under software control so I couldn't measure the NMI high time with any great certainty.

I built an NMI latch using half a 74LS74, this is edge triggered and is arranged in such a way that it is reset under program control, this is done as the first operation in the NMI routine after saving the registers. Guess what? It worked! The program now fell over in a completely new and subtle way - doh!

The final answer seems to have a lot to do with how the 3Com cards respond in 8 bit mode and what happens when you poll status registers.

While I'm not thrilled with the fix, it means the processor sitting idle for 1ms on every packet, it is working at the moment. Before work I left the Vic 20 being repeatedly pinged (ICMP echo request) by three PCs and it hadn't missed a beat in 40 minutes or so.

All this will eventually be posted to my site, I've done 20 or so pages (including picture pages) on this so far.

Who'd have thought getting ISA cards to work with the 6502 bus would be so fraught?

Lee.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?