Able to transfer data from 6551 to computer, but not back

[ioncannon]

Have transferred my homebrew computer from breadboard to protoboard, and it seems everything is working. There are only two problems. First I didn't soder the 1.8mhz crystal, instead wrapped the appropriate wires. However sometimes if the right pin of the crystal is touched, the connection freezes. Also the bigger problem, is I can send data out from TX, but RX is not recieving any data. I have a loop waiting for data that looks like this

Code: Select all

ACIA_WAIT_RX:
	LDA	$2001
	AND	#$08	
	BEQ	ACIA_WAIT_RX	
	RTS

and the cpu freezes in a infinite loop. The wires I have hooked up are RTS, CTS, RX, TX, and Signal/Shield grounds.

[GARTHWILSON]

Rmember the DCD\ input must be low for the receiver to operate.

For a faster loop (not that it really matters this time), you can use BIT. It's faster because the same instruction that does the fetching also does the ANDing, altering only the status register (bits N, V, and Z) and not the accumulator:

Code: Select all

   LDA  #8
ACIA_WAIT_RX:
   BIT  $2001
   BEQ  ACIA_WAIT_RX
   RTS

[BillO]

I've had problems with 6551s with the cpu at at 1.8Mhz. Not sure if this is your case or not. They need a little time to do their internal reset and some seem to do this quicker than others. I generally put in a 10ms delay after power-up to let everything settle down before sending any configuration to the 6551. 10ms is way more than required and you could trim that down substantially if start-up time is an issue.

Here is the code I use. Not pretty, but accurate.

Code: Select all

;
; TIC - a timer routine.
; Number of loops to run is expected in Y
; Based on the 1.8432MHz clock in the OMS-02 controller
; One iteration of TIC is ~43us
; Calling TIC from DELAY with $E9 in Y gives a time of 10ms
;   Takes 12 cycles to call and return
;   Plus 14 additional cycles to call TRIM
;   So, total time (T) when called with $E9 in Y gives:
;   T=232*79+78+12+14=18432 cycles
;
;
TIC      lda #$08                   ; Set the inner loop count(2 cycles)
         sta $FD                    ; Store in $FD (3 cycles)
         nop                        ;
         nop                        ;
         nop                        ; 3 nops adds 6 cycles to outer loop
TBLOOP   dec $FD                    ; Decrement inner loop counter(5 cycles)
         bne TBLOOP                 ; Loop if not done (3 cycles if looping, 2 cycles if not)
                                    ; Whole inner loop is 7*(5+3)+7=63 cycles in length
         dey                        ; (2 cycles)
         bne TIC                    ; (3 cycles if looping, 2 cycles if not)
                                    ; Each outer loop is 16+63=79 cycles, except last is 78 cycles
         jsr TRIM                   ; This adds 14 cycles
         rts                        ; (6 cycles)

;
; TRIM - calling this wastes 14 cycles
;
TRIM     nop
         rts

[ioncannon]

GARTHWILSON wrote:

Rmember the DCD\ input must be low for the receiver to operate.

For a faster loop (not that it really matters this time), you can use BIT. It's faster because the same instruction that does the fetching also does the ANDing, altering only the status register (bits N, V, and Z) and not the accumulator:

Code: Select all

   LDA  #8
ACIA_WAIT_RX:
   BIT  $2001
   BEQ  ACIA_WAIT_RX
   RTS

Ahh garth, that was the problem. I was using this schematic http://members.multimania.co.uk/leeedav ... index.html which ties the DCD and DSR pins high, yet in the text it says it's tied low. Will check if it fixes it.

Update: Alright it works! Was actually getting real pissed by Putty because I couldn't figure out if the output was from the computer or local echo (even with it off), so I just incremented the received input to test. Cool.

[leeeeee]

Quote:

Ahh garth, that was the problem. I was using this schematic http://members.multimania.co.uk/leeedav ... index.html which ties the DCD and DSR pins high, yet in the text it says it's tied low.

It shows them tied low in the schematic. Ok, so it could be a little bit clearer.