BitWise wrote:
I was looking at some 40MIPS 3V3 PIC 33FJ128GP802 devices [...] They can be programmed to appear as a 4 byte memory area in the hosts address map. Reads and writes to the chip trigger interrupts so you can update the contents.
It's an appealing setup. A similar scheme was used in the 8741, a member of the 1970s Intel MCS-48 family (famous for the ubiquitous 8048 keyboard controller). The 8741 variant was aptly billed as a "
Universal Peripheral Interface."
The 8741's host/slave shared memory region was only two bytes in size: a data register, and a command/status register. Despite the seemingly limited interface, a great deal becomes possible if you're willing to explore the envelope. For example, as Big Ed notes, "for each data transfer, you need some handshaking to say that the write is done, and
the reader has to signal that it's finished with the data." But I think he'd agree that the "finished" signal from the reader can be eliminated -- turbocharging the transfer -- if reader timing can be guaranteed. That guarantee might not be difficult to achieve, given that you have an entire dedicated cpu at your disposal. (I'm envisioning a block transfer, with simplified handshaking on the innermost loop only.)
Garth Wilson wrote:
What can be a disadvantage sometimes is that having these interfaces another level removed from the main processor, you may incur unwanted delays in getting the data back and forth.
Yes. Another consideration is access to the code. Presumably your host system has some way to load new application software, but changes to the code in the slave cpu are likely to be comparatively inconvenient (and hopefully infrequent).
-- Jeff
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