WDC has posted an updated data sheet for the W65C816S, dated September 13, 2010. There are still some errors in it but it's better than the previous version.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

With all due respect, I've seen "updated" 6502 spec sheets. Sometimes they are "repealled" and an older spec sheet is present afterwards...

This is not a criticism, just an observation.

It's good WDC at least shows the effort to update spec's.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

There is an errata on 9/13/10 '816 data sheet at http://6502org.wikidot.com/errata-datasheets-w65c816s , and on the 10/19/10 '02 data sheet at http://6502org.wikidot.com/errata-datasheets-w65c02s , thanks, I suspect, to Bruce. I have not checked them point for point, but he's really good at such details. Bruce (or whoever wrote and posted them), have you alerted Bill Mensch?

I had sent a copy of the '816 errata to WDC and they did acknowledge it. So far, none of it appears to have made into the current data sheet.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Yes, I wrote the errata. If you look at the history (there's a link at the bottom of the page), you can see who made what revisions (in this case, all me so far). You can also see when the revisions were made. You may be able to guess what prompted the latest update.

No, I have not alerted anyone at WDC. The original impetus for creating was when the '816 datasheet had (apparently) the 65802 timing diagram, and we had all that forum activity from people who were (understandably) confused by the lack of a bank address being multiplexed on the bus. While I was at it, I went through the entire datasheet to catch as much as I could. The timing diagram has been fixed. Several of the remaining items are very, very minor (e.g. section numbering). I've kept updating the errata page mostly because I am picky. When I update the errata, I check to see if the things that are listed were fixed, but I don't always review the entire datasheet looking for fresh issues. I didn't this last time.

Do my EyE's deceive me or do I see a QFP style package for my beloved 65C02 on the new WDC datasheet???!!!!! The gods have ears!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

They used to have the PQFP but quit selling it some time back. You'll have to check on WDC's order page and see if it's available. The fact that it became unavailable is, IIRC, why Daryl did not go through with making the 40-pin DIP 65802-like replacement which could have been put in a 6502 socket and used an '816. The project was discussed starting here.

It's not available yet! or is it?

There is a 3rd listing for a W65C02S6PL–14 listed for $5.07, but no pic...
Similarly for the '816!! OOOHH , OH! I may be making a call soon!

But that is a new addition, or RE-addition, to the datasheet compared to the one I have from July '09...

That QFP is 1/4 the size of the PLCC package. That's alot of space, especially on a 3.8"x2.5" protoype board.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Make sure you count the fact that the PQFP's leads stick way out instead of being curled under. When you compare the land patterns, the PQFP takes about 1/2 the number of square inches as the PLCC. The 44-pin PQFP takes the same amount of room as the 32-pin PLCC.

IC's in QFP packages are meant for soldering (i.e. "permanent" connections). I know you post here for the benefit of others Garth, especially since you started this thread.

IC's in PLCC are meant for socketing/soldering. Primarily socketing, which is good for IC's that may have to be replaced/upgraded/easily wired...

However, they may conceivably have another advantage...

Since the package is so much larger than the die itself, compared to QFP, it may be advantageous to use PLCC for heat dissipation/speed...

Still, I would really like to use the QFP package, even if it may mean a speed sacrifice. The sacrifice being a switch from: a WDC65C02 PLCC @3.3V running @20MHz, to a WDC65C02 QFP @3.3V running @the rated 14MHz.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Ah yes, I forgot about the socket, if indeed you wanted to socket it. I don't know of any socket for PQFP though, so the only way to compare apples to apples is to solder both directly.


The rating for 3.3V is only 8MHz. It's nice they put the typical f(MAX) in the datasheet though, and extrapolating it out to 5V makes it look like it could do 24MHz. Absolute max is 7V. Then you could put a peltier device on it to bring its temperature down to around freezing, and, I wonder...

I see about 14MHz for 3.3V on the WDC65C02 specsheet. This "spec" has not changed since the '09 WDC65C02 datasheet...

What is the DATE on your spec's Garth?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The one on WDC's website, page 25, near the top. Right under 5.0 +/-5%, it says 14MHz. Under 3.3V +/-10%, it says 8MHz.

I was referring to Fig. 6-2: VDD vs. FMax on the bottom of pg. 24...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

That's a typical absolute max speed the processor will run at, but it's definitely not guaranteed to, and it won't meet the timing spec.s at that speed when its almost to crash anyway. I like to turn up the speed with a variable-frequency oscillator until it has trouble, then back it down a bit for some safety margin for actual use. Fortunately WDC's specs are usually quite conservative, and the parts can normally do better than they say.