I didn't want to hijack the "Wait-States with a GAL" thread, so I thought it's better to start a new one:


This is correct. If you have to interface with 5V CMOS level logic the XL series is a no-go. So far this hasn't been a problem for me as I only used devices with TTL level inputs.


I'm also looking more and more at Atmel, especially since Lattice discontinued the whole GAL series a few months ago.

<mode=rant>
I've been using Lattice 16V8 and 22V10s a lot before and some 5 years ago I used the Lattice mach 4A5 series (in PLCC).

The 4A5s were really nice chips, the 4A5-64/32 for example had programmable input latches that didn't eat up registers. A nice feature which I hadn't found in Xilinx and Altera chips and which saved one of my designs :-). Now the 4A5s are hard to get and expensive as hell: Farnell wants 20 EUR plus taxes for a 4A5-64/32. A Xilinx XC9572XL costs 2.4 EUR - this is a factor 8! Lattice doesn't have a replacement for the 4A5 series, only for the 4A3s and the recommended 4000V comes in TQFP :-(

So currently I'm using more and more Xilinx XC95..XL in PLCC. With a PLCC socket I can use them on a prototype board, just need an additional 3.3V regulator.

As for quick-prototyping using a GAL in DIP surely is nicer to handle than a PLCC44 socket. But the XC9536XL or XC9572XL are cheaper than 22V10s (approx. a factor of 2-4), are a lot more flexible and can hold a lot more of logic and are in-system-programmable with a simple JTAG cable.

I just hope Xilinx doesn't follow the Lattice route and discontinues the XC95..XL series too soon...
</mode=rant>

so long,

Hias

SHHHH! A simple JTAG cable? what is that?!

5V Xilinx CPLD parts will go the way of 70's Disco I think. No demand. Oh well.

On to the next voltage level!

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

I'll tell you a secret if you promise me not to tell anyone else :-)))

The simplest JTAG interface I built so far was just 4 wires connected to the 6520 PIA of my Atari 800XL. Compiling ispVMSystem Embedded using cc65 was easier than I thought and programming a Lattice 4A5-64/32 worked fine (although it took something like 15 minutes or so).

Unfortunately our original plan (having a simple JTAG cable that plugs into the Atari's joystick port) didn't work as Atari decided to put inductors and capacitors between the PIA and the joystick port which ruined signal edges. But connecting the wires directly to the PIA worked fine :-)

so long,

Hias

I have one of those. I've used it with FPGAs and CPLDs. I already had parallel cable, but my new laptop didn't have a parallel port anymore, so I got this USB cable instead. I hated having to replace all my parallel gear, but then I noticed this cable was a lot faster.

http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-USB

Arlet,
just for clarification, is your USB cable from Digilent OK for Xilinx parts generally (or just Digilent boards) - and, do you know if it can be used with Linux?

Hias,
An excellent plan! Never mind the lack of parallel printer ports on modern PCs - anyone in possession of a 6520 or 6522 is only ... well, it probably takes quite some expertise, but is only a matter of software! Personally I use an old laptop running TinyCore linux from RAM, with sshfs to mount the Xilinx tools from elsewhere. But when that laptop gives up, I know what to do!

Hias, if you have or know of a writeup or some resources, please spread some links around. Programming the programmable parts using a 6502-based system has a nice feel to it. (How did you get the bitstream onto the Atari - floppy disk?)

Casting around for cheap minimal cross-platform solutions, I note that I have a USB-I2C interface module which doesn't quite have the I/O to do JTAG, but it looks like the USB-ISS might be capable for about £20
http://www.robot-electronics.co.uk/acat ... .html#a101

Cheers
Ed

Ed,

I've used the Digilent cable on a couple of my own boards, with Xilinx FPGAs, and it worked fine. The JTAG signals go straight into the FPGA and/or PROM, so it doesn't really matter what board you have, as long as these signals are the same.

I haven't looked for a Linux driver. I just use a Windows laptop for programming.

Hi Ed!


I found the old source code, just have to figure out what exactly I did some 5 years ago :-) I'll pack it up and upload it later.

Back then I used a floppy disk image (served by my PC running AtariSIO, emulating an Atari disk drive) to get the data to my Atari. The compiled software and the PLD programming data wasn't too big - the software was some 15k and the "program+verify" data also was some 15k.

so long,

Hias

Here's my old source code:
http://www.horus.com/~hias/tmp/ispvm-050910.zip

I hope this was the last, working, version, not 100% sure and ATM I cannot verify it. But at least it compiles with the current cc65 without warnings :-)

It seems I have played with various delay functions, the functions in the asm.s file seem to be unused, instead I seem to be using ANTIC WSYNC (wait-for-hsync, which halts the CPU until the end of the current scanline). This part must certainly be replaced by some other code for other platforms.

The low-level stuff (i.e. interfacing with the PIA) is in hardware.c plus the pin-definitions are in VMEDefinitions.h. README.txt just contains a short description which PIA pin is connected to which JTAG wire. But experienced users could also be able to retrieve this information just from VMEDefinitions.h :-)

As a reference I included the (maybe) original code in the "orig" directory. I'm not 100% sure if this is all of the original Lattice code, just found the "orig" dir on my harddrive and thought it would be helpful as a reference so you can diff against it.

While analyzing the code I found some interesting part in vmopcode.h:


Then I tried to pass a Xilinx XC95144XL SVF file to svf2vme12 on my Linux box and got some output together with the message "PASS" :-) Not sure if this will really work, and if the VME file-format is still the same as back in 2005, but this could be some starting point :-)

Ah, another note: IIRC I didn't spend much time on optimizing the code back then, so it could well be that the programming/verifying time could be significantly lowered.

so long,

Hias

Hias,
I was re-reading your original post where you said you used Xilinx XC95xxxXL series, which are the 3.3V devices. But it sounded like you were interfacing to 5V TTL?

If this is true, why did you not use a regular XC95xxx, which are 5V devices?

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Arlet, I think he was describing a custom interface like discussed [url=http://forum.6502.org/viewtopic.php?t=1503&postdays=0&postorder=asc&start=80[/url]here[/url], except Hias was interfacing directly from an atari800 to a Lattice CPLD via his custom JTAG.



BigEd, I can confirm with Arlet that Digilent JTAG cables are made to interface to MOST Xilinx PLA's.

I bought a Digilint board with a Coolrunner II, and a XC9536. It came with ISE 9.1 and a parallel JTAG cable($12US). I've been using this same JTAG cable to program all CPLD's and FPGA's in my PWA project to date.

The only spec to pay attention to, are the voltages spec'd in the JTAG cable (usually written on the shrinkwrap on the 6-pin header). This is because some of the newer FPGA's are lower core volts and therefore not compatible (i.e<1.8V)...

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

There were 2 reasons: availability and price.

I used XC9536 and XC9572 (without -XL, native 5V) before and really didn't like the idea of using -XLs (3.3V) with my 5V Ataris. I feared I could run into troubles due to the mixed-voltage stuff. Then some 2 years ago a friend forced me to use a XC9536XL and it did work well.

XC9536 and XC9572 are still available both as 5V and 3.3V (XL), but the 5V versions cost 2-3 times as much as the 3.3V XLs.

For my current project, a new version of my Turbo Freezer, I needed a XC95144 (both for the registers and I/Os) which isn't available (here) in 5V - so a 3.3V XC95144XL was the only option.

Long story short: don't be afraid to use (Xilinx) 3.3V PLDs with 5V tolerant I/Os in a 5V design. The datasheets say it works and I also say it works :-)


BTW: Just bought a WD TV Live yesterday and when browsing through the internet radio stations I couldn't find any alternative/indie rock stations, but I found Disco, Soul and Funk stations! So I guess there seems to be more market for 70's Disco than for 5V PLDs :-)))

so long,

Hias

My current setup is a homebrew Lattice cable (with a '244 line driver) connected to the parallel port of my Linux box. I use UrJTAG to program the SVF files into Lattice and Xilinx PLDs.

So far I had quite mixed results with the very simple cables (only wires plus series resistors connecting to the parallel port). I have one here that works fine with the onboard parallel ports of my PCs, but not with the parallel ports on addon cards. The Lattice cable with the line driver works fine both with on-board and addon parallel ports.


This is another issue, of course. The simpler cables will usually only work with 5V and maybe 3.3V, but not with lower voltages.

Also, when programming large FPGAs (which I haven't done yet) USB cables (for example FT2232 based cables) are preferrable as they are often a lot faster than bit-banging a parallel port on the PC. At least this is what I read on the 'net so far.

so long,

Hias

So, the summary position on cables, at least for Xilinx parts, seems to be
- watch out for the voltage levels if you have a low-voltage FPGA
- USB cables are fastest and cross-platform, a grey market one is cheaper than one from the USA or EU.
- parallel-port cables are cheap, cross platform, can be made yourself, but you need a real parallel port - not a USB-printer adapter - and if you build your own unbuffered design you might have signal integrity trouble.
- bit-banging from any 4-pin port is possible, but might be slow and might take some ingenuity to get it working.

(If this isn't quite right, let me know and I'll edit it.)

Cheers
Ed

Just for the CYA move here, because the Spartan 3 family is the newest I've ever used and they're already a mature product: I refer these links to anyone wanting to experiment with the newer Xilinx FPGA's & CPLD's... The USB adapter here from Digilent apparently covers "everything" Xilinx.

http://digilentinc.com/Products/Detail. ... P-USB-JTAG


http://www.xilinx.com/support/documenta ... /ds300.pdf

The Xilinx link is present inside of the Digilent link...

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502