ARGGH. So this "1st chapter" is going to be the 65002? which is 8-bit external data bus?
Wouldn't it be easier starting with a 16 bit foundation? Which begs the question should this new version of
yours be backwards compatible with the NMOS6502.
Would be nice to add a polling feature to this forum for questions like these.
I for one would like to see a TRUE 16-bit 6502, forget backwards compatibility. Also add more registers, up to 16? maybe more?
Add 1 more accumulator, maybe add another ALU to support it.
True 16 bit would mean a 65K zero page? MAKE IT INTERNAL to the FPGA.
Also, more importantly, will it be a 5V core? 3.3V? SRAM & EEPROMs currently available and prices need to be considered... 5V is dying quickly. If it can fit onto an older Spartan 2, it could run @3.3V and still have 5V input tolerance, (5V output tolerance is claimed by some on Xilinx forums). Thus one's choices of RAM & EEPROM are expanded, although in the wrong direction (less memory).
Quick lookup on Digikey, 1Mx16 RAMs are available for $40 each. (2Mx16 are only available in BGA packages). Note that most of these types of "wide" RAM's only come in 3.3V.
Also, (forgive me for rambling on), but I don't think it would be too difficult to have some dedicated memory I/O for built in interface standards (think of the 6510). You could start straight off with USB/I2C/PS2, maybe even EIDE. And need less than 255 dedicated registers.
This is what I am asking Santa for.
![Laughing :lol:](./images/smilies/icon_lol.gif)
This is WAY too much to ask for isn't it?