I wonder if the speed is based on the core running alone or with a basic memory system. At 34 MHz, the cycle time is 29.4 ns. It might be more of a matter of having a fast-enough memory access system.
Just a thought...
Daryl
MyCPU - not a TTL 6502
Good point -- I hadn't thought of that he might be measuring a complete system performance.
One of these days, I'll explore some interesting-looking processor architectures. Stack-architecture CPUs are easy to make, of course. I'm particularly interested in transport-triggered architectures as well. And, of course, the challenge of making a 6502/65816-like CPU with a pipeline and a direct-page cache to try and push single-cycle instruction execution (on average, of course).
I suppose I could play around with the Verilog now, even without having an FPGA to test it on. Just trying to simulate should be enough for now. I'll install Icarus again and see what trivialities I can come up with.
One of these days, I'll explore some interesting-looking processor architectures. Stack-architecture CPUs are easy to make, of course. I'm particularly interested in transport-triggered architectures as well. And, of course, the challenge of making a 6502/65816-like CPU with a pipeline and a direct-page cache to try and push single-cycle instruction execution (on average, of course).
I suppose I could play around with the Verilog now, even without having an FPGA to test it on. Just trying to simulate should be enough for now. I'll install Icarus again and see what trivialities I can come up with.
Found a patent I'd mentioned previously - the one which Commodore owned, about implementing single-cycle opcodes.
"System for accelerating execution of program instructions by a microprocessor"
Issued 1992, inventors Gardei and Hauck.
"System for accelerating execution of program instructions by a microprocessor"
Issued 1992, inventors Gardei and Hauck.
BigEd wrote:
Looking at the 65ce02 datasheet (pdf) we see
and we also see some additional busses in the block diagram (see below)
The same datasheet shows the reduced cycle counts, including many single-cycle instructions (and no page-crossing penalties). Garth has previously mentioned patents covering the elimination of dead cycles, but I haven't yet discovered the patent numbers.
Quote:
A unique design feature allows [Address registers] ADL and ADH to store indirect address vectors while [Address Counters] ABL and ABH function as counters, thus relieving the ALU from internal address fetches and increasing throughput
The same datasheet shows the reduced cycle counts, including many single-cycle instructions (and no page-crossing penalties). Garth has previously mentioned patents covering the elimination of dead cycles, but I haven't yet discovered the patent numbers.
