Custom chips at $100 each (or $30, or $20 at quantity)

[BigEd]

As noted previously, there's an initiative to make chips using a fully open source chip design flow, which is presently accepting submissions of open-source chip designs for free fabrication later this year.

As last year, as I understand it, they are accepting up to about 40 designs (to be selected by them if over-subscribed) and will return 50 packaged chips. I think the package is a 100 pin mini-BGA, and there are 37 I/Os available. The process is 130nm, and the I/Os are 5v tolerant. The allocation for the design is 10mm2, which is apparently up to a million gates - a great deal more than the FPGAs we deal with, although they come with onchip RAM too, so with that it might come out even. Who knows.

One interesting piece of news in this video update is that the same process is being offered commercially: 100 chips for $10k.

TBH, I think it's quite a stretch beyond an FPGA design: and having a design work on FPGA would be a pre-requisite, in practice, because for $10k you certainly want to have tested out your design. But, it's not entirely out of reach, and anyone who's got an FPGA design up and running is probably able to learn how to work their way through a chip flow.

[BigEd]

BigEd wrote:

I think the package is a 100 pin mini-BGA, and there are 37 I/Os available. The process is 130nm, and the I/Os are 5v tolerant. The allocation for the design is 10mm2...

One interesting piece of news ... the same process is being offered commercially: 100 chips for $10k.

Quick update (Edit: new location here) on the commercial offering:

• $10k gets you either 100 QFN or 300 WCSP packaged parts
  $20k gets you 1000 WCSP parts

So that's $20 each, for a custom chip in a tiny package with nearly 40 I/Os (5V tolerant). A pretty good deal, except for the volume: not so many retrocomputing project can hope for quantity of 1000.

One interesting possibility is to design multi-purpose chips which share I/Os between macro functions, at the cost of a few I/Os to determine which role each chip should play.

[BigDumbDinosaur]

Enticing as it may initially sound, the economics aren't there, except for professional operations in which a product development budget is available to support such prototyping. For us mere mortals, synthesizing in an FPGA is still the way to go for a one-off design. As you say, it's unlikely a hobbyist is going to need hundreds of copies of his/her design.

That said, it's likely the cost for small-run chip production will come down over time and the minimums required to get your custom design produced will follow. We've already seen this in small-run PCB production, although the latter is much less technically-complicated than producing a working chip. Nevertheless, history says it will happen with chips, although probably not in my lifetime.

[unclouded]

BigDumbDinosaur wrote:

As you say, it's unlikely a hobbyist is going to need hundreds of copies of his/her design.

I think what BigEd is saying is that if there were a design that included a 65SPI, a hardware I2C master, a wait state generator, a couple of 6551s without the transmit bug, and a DRAM controller then you might be able to find 1,000 takers. It wouldn't be necessary to use all of the functions in a given design. Maybe in a few years time it will be $10 with a MOQ of 100.

How hobbyist friendly is WCSP? How much would a PCBA house want to put it on a DIP40 breakout board?

[BigEd]

Indeed, that's my thinking: lots of room inside the chip, just need to use a few pins to determine function. If the chip includes some interesting or rare functions (SID...) then it might have sufficient value.

The WCSP seems to be a bare square of silicon with 100 solder bumps: very very much a surface mount device, so you need an oven (or similar) and probably a carrier board to provide a more friendly interface.

For me, this recent development shows progress in a good direction, but not yet reaching the point of being accessible enough. There was a time when FPGAs, or surface mount devices, or four-layer PCBs, were out of reach, and now they are well within reach. So it might be with custom silicon.

[BigDumbDinosaur]

unclouded wrote:

How hobbyist friendly is WCSP? How much would a PCBA house want to put it on a DIP40 breakout board?

All those functions in your shopping list would likely require more than 40 pins to interface to the remainder of the system. PLCC is hobby-friendly if used with a socket, and offers many more pins.

However, I think my argument stands. The economics aren't there...yet, just as they weren't with four-layer PCBs 20 years ago.

As for the multiple 6551s (with or without the bugs), what a waste of good silicon. A single NXP DUART would do the job in superior fashion—without the bugs.

[plasmo]

unclouded wrote:

I think what BigEd is saying is that if there were a design that included a 65SPI, a hardware I2C master, a wait state generator, a couple of 6551s without the transmit bug, and a DRAM controller then you might be able to find 1,000 takers. It wouldn't be necessary to use all of the functions in a given design. Maybe in a few years time it will be $10 with a MOQ of 100.

The functionalities you mentioned (DRAM controller, I2C, SPI, wait state, serial port) are not very complex and can be implemented in modest 5V CPLD like ATF1508 which is $4.62 in quantity of 1 from Mouser. DRAM controller does need quite a bit of pins, so a 100-pin SMT is probably needed to do the various functions. I've implemented something like that for a Z80 SBC, ZRC. It has 2megabyte DRAM, DRAM controller, bank select logic, 6850 serial port, I2C bus, compact flash interface, driver for pixel-addressable LED (WS2812B), and importantly, a fast 64-byte bootstrap ROM. A lot of features can be packed into a small board with help of the CPLD.
Bill

[BigEd]

unclouded wrote:

I think what BigEd is saying is that if there were a design that included a 65SPI, a hardware I2C master, a wait state generator, a couple of 6551s without the transmit bug, and a DRAM controller then you might be able to find 1,000 takers. It wouldn't be necessary to use all of the functions in a given design. Maybe in a few years time it will be $10 with a MOQ of 100.

Hmm, reading this more carefully it might not quite be what I'm thinking: in my picture, there's no case for "a couple of 6551s" because in my picture, each chip will be configured by tie-offs to one particular function. So, it's a multi-purpose chip in one sense, but not in another. I'm not thinking of mopping up a lot of glue or a lot of peripherals: for one reason, not enough I/Os, and for another reason, it pins down a specific idea of a system design.

Many 80s machines have some custom circuits or no-longer-available VLSI chips: those chips can presently be salvaged from existing machines, preferably broken ones, but that's not a long term answer. But all those chips have been modelled, to some degree, in projects like MAME if nowhere else. Many of them exist as open source HDL already. For some, more work is needed.

Of course there's another, different story: create a wonderful system design which needs only 36 I/Os and sell it in quantity, with some reason why an FPGA wouldn't have done the job. It's the selling in quantity which is the hurdle.

Another story again is to be happy to spend $10k on one chip just for yourself, but that's a special case!

[GARTHWILSON]

unclouded wrote:

I think what BigEd is saying is that if there were a design that included a 65SPI, a hardware I2C master, a wait state generator, a couple of 6551s without the transmit bug, and a DRAM controller then you might be able to find 1,000 takers. It wouldn't be necessary to use all of the functions in a given design. Maybe in a few years time it will be $10 with a MOQ of 100.

How hobbyist friendly is WCSP? How much would a PCBA house want to put it on a DIP40 breakout board?

Take a look at what WDC is offering in the MyMENSCH FPGAs microcontrollers, at https://wdc65xx.com/fpga-microcontrollers/ . There's no DRAM controller or wait states, but they do have SPI and I²C master, multiple UARTs and the function of multiple VIAs, a 12-bit A/D converter, onboard hardware multiplier, the '816 version has an onboard hardware divider too, and more. I have not looked into them much yet, but I have been meaning to do so if I ever catch up.

[BigEd]

I'll bump this thread because time has passed and things have changed.

I see there's an outfit called wafer.space who recently completed a successful crowdfunding campaign. On offer were 1000 custom chips to your design, for $8500.

So, custom silicon is now looking like $10 per chip, if you have (or can raise) about $10k dollars. That's within scope for a crowdfunding, probably, or perhaps for some small collective of relatively well-off hobbyists.

One of the projects on the first run is a Z80 in a 40 pin DIP format (chip on board.)

(As noted upthread, it feels to me like an attractive approach would be a multi-design which can somehow be configured as one of a number of 40-pin chips. You'd need at least one spare pin to manage the configuration, if you want it static.)

Of course, custom silicon makes sense when for some reason FPGAs are not a good solution. The skills to make a custom chip using this kind of offering are very much like the skills needed to make a successful design on FPGA.

[John West]

BigEd wrote:

(As noted upthread, it feels to me like an attractive approach would be a multi-design which can somehow be configured as one of a number of 40-pin chips. You'd need at least one spare pin to manage the configuration, if you want it static.)

That sort-of exists in the form of Tiny Tapeout https://tinytapeout.com/. The designs are truly tiny, and you're limited to 8 input + 8 output + 8 bidirectional pins. But it's cheap enough for hobbyists. People are submitting experimental designs just to see if they work.

I remember some discussion on the Discord a while ago among people organising something closer to what you're talking about - a smaller number of (more expensive) larger designs. I'm pretty sure there was a 6502 in there. There was definitely a Z80. I think that was before Efabless folded, and I don't know what happened with it.

[BigEd]

(I think this latest adventure is a response to the failure of efabless.)

[Agumander]

BigEd wrote:

Of course, custom silicon makes sense when for some reason FPGAs are not a good solution.

One interesting thing I noticed while trying to understand the PDK docs is that it seems to support making a 5V chip, which has very limited support on similar priced FPGAs that you can easily source today.

[BigEd]

Good point, 5V is a good place to be, for retro projects!