Absolute Indexed Addressing - To "fixup" ADH or not

Anarcholepsy · Post by **Anarcholepsy** » Tue Mar 17, 2026 6:26 am

Hello again, friends.

I have recently been studying the data path controls for the 6502 absolute indexed addressing mode instructions. As I'm sure we all know, when an instruction in this addressing mode crosses a page boundry, the 6502 takes one cycle to "fix up" the upper bytes of the address. For the memory reading instructions (LDA/X/Y), this cycle (T4) is optional - skipping straight from T3 -> T0 if there is no page crossing - but for several other instructions (i.e. STA and the RMW instructions) in this addressing mode, this fixup cycle always occurs even when there is no fixup to do. (Of course, this was remedied for most of these instructions on later processors, with some exceptions)

This has led me to a slight confusion which I hope you might be able to help with - what, exactly, is it that triggers this fixup to happen? Obviously I understand that it's caused by a page being crossed, I'm asking about the internal signals that determine this, and their timing(s). Here's some examples to demonstrate my thought process:

For the ones where T4 is optional, such as LDA/X/Y Absolute Indexed - well, it's pretty easy to understand what's probably happening here I think? During T3 Phi2, if the ALU carry out signal is set, the PLA selects T4, and once the instruction is in T4 the fixup always has to happen, you could say by definition.

However, T4 always happens for STA, so something else has to determine whether or not ADH is incremented, but I don't quite see how the timing lines up.

While searching for this subject, I came upon this old topic, which gave me a lot of help towards this, especially the info that the "fixed-up" ADH is always calculated, even if the page isn't crossed - the difference is that the ADH/ABH data path node is active for the page crossing scenario, but not otherwise. (I have to say, I think that this is a pretty elegant way of doing it, if the designers couldn't avoid the T4 cycle at the time)

I'm still left with the question - what is causing ADH/ABH to be active (or not) on this timing? The obvious answer is the ALU carry out and I think it probably is that, but I still have some parts I don't quite get, so after all of this preamble here's the actual meat of the question:

My understanding is that by the time ADH/ABH can potentially be latched, the ALU carry out from the previous cycle (T3) will have been replaced with the result from the current one (T4)? As shown in the second picture I've uploaded, alucout is 0 in Phi2 of T4 (cycle 7) of STA Abs X, which is the half-cycle that latches ADH/ABH or not, but the fix up does happen. Furthermore, returning to the first image of LDA Abs X, the situation is reversed - alucout is 0 in T3 Phi1, only being set to 1 in Phi2. But the processor proceeds to T4, so it must be using the Phi2 value in that case (if it is indeed directly using ALU carry out and not an intermediary).

Is the CPU able to use both the Phi1 and Phi2 values from the ALU carry out when deciding on the next data path nodes? Or is there some other signal that's being set somewhere?