Hi,
I am trying to understand some aspect with the Arlet's 6502 core that may have been discussed before. Anyway its related to how the load_reg is set and the use of it to set write_register.
The thing is that load_reg is assigned with a non-blocking assignment (so it can be delayed). Now that is usually fine, but if the next instruction is a write register instruction, write_register uses load_reg.
This is probably also fine, but in some instances the load_reg could become delayed. For example with LDA $1234,X, which would, if the next instruction is a STA then cause the write_register to fire AXYS[regsel].
As said, this is usually not a problem, but if timing gets constrained I am thinking that it may give rise to some problematic register update. Or maybe I am just being paranoid. I was originally thinking around the RDY assertion when I started thinking of this.
Anyway, could it be an idea to gate the write_register?
Arlet core register timing
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WillisBlackburn
- Posts: 51
- Joined: 14 Aug 2021
Re: Arlet core register timing
The short answer is: I don't know. It would make sense that if the assignment to load_reg were delayed, then everything else, including processing of the following instruction that used it, would also be delayed.
But I would not change the code based only a suspicion that something might be wrong and that the change might fix it. If there is really an issue with timing or anything else, create a test bench that exposes it, then you will have both confirmed that it is a problem and built a tool that can verify the solution.
But I would not change the code based only a suspicion that something might be wrong and that the change might fix it. If there is really an issue with timing or anything else, create a test bench that exposes it, then you will have both confirmed that it is a problem and built a tool that can verify the solution.
Re: Arlet core register timing
I believe Arlet's core has seen a lot of use, so I'd be a bit surprised if there was a problem. (But I haven't investigated this latest observation.)
Re: Arlet core register timing
Hi!
I suspect you are not reading the verilog code correctly.
"load_reg" uses a non-blocking assignment (<=) inside an always @(posedge clk) block; making it a registered signal, stable throughout the clock cycle.
"write_register" uses a blocking assignment (=) inside an always @* block; making it combinational, which is correct and carries standard timing constraints.
Neither of these is problematic.
Have Fun!
I suspect you are not reading the verilog code correctly.
"load_reg" uses a non-blocking assignment (<=) inside an always @(posedge clk) block; making it a registered signal, stable throughout the clock cycle.
"write_register" uses a blocking assignment (=) inside an always @* block; making it combinational, which is correct and carries standard timing constraints.
Neither of these is problematic.
Have Fun!