Contemplating DMA
Re: Contemplating DMA
Even when switching between unrelated clocks of comparable speed, you need to take care. There are techniques for glitch-free clock switching, but if you're not careful, a device could see two edges very close together - one from the old clock and the next from the new. You need a circuit which can see both clocks to mediate between them at a safe time.
Re: Contemplating DMA
I suspect only a latch on the appropriate edge of ph2 to trigger BE and RDY and another latch at the end of the transfer to deassert them. There's no action during the DMA and the processor doesn't even see it; it's asleep.
But as mentioned, that's currently not in the game plan.
Neil
But as mentioned, that's currently not in the game plan.
Neil
Re: Contemplating DMA
Here's a first cut at a circuit diagram; it still needs some odds and ends tidying up, but any input before then is appreciated.
The idea is that when the processor writes to the DMASTART address, it triggers U5 which starts the cycle; the counters U6,7,8 count to 512 and then reset. During this time, the 65c02 is halted with BE holding the bus three-stated. U10 and 11 switch the counter output and the top seven bits of U9 - latched from the data bus when DMASTART was written - to the memory address bus to give the target address.
At the same time, the CF address is tied to zero, and it's ~RD and ~WR input are replace with a locally generated signal - ICs 1,3, and 4 and a modified signal replaces system R/~W.
Before starting the DMA, the processor writes the LBA to the CF, starts the transfer, and waits until the CF is ready to transfer. Then it writes the DMASTART; the low bit of the page address defines whether this is a CF-RAM or RAM-CF transfer.
For writes to the CF, R/~W stays high to read memory, and ~WR pulses once per clock to force the CF write. ~RD stays high. To read, ~WR stays high and R/~W pulses low once per clock, along with ~RD. I _think_ that gives me a valid transfer time at 1.8MHz; the data appears some time after ~RD goes low and is written to RAM on the rising edge.
At the end of the transfer, the timers stop, the flip-flop resets, BE is raised and RDY deasserted. The processor starts and has the data available from the next instruction.
I hope...
Neil
The idea is that when the processor writes to the DMASTART address, it triggers U5 which starts the cycle; the counters U6,7,8 count to 512 and then reset. During this time, the 65c02 is halted with BE holding the bus three-stated. U10 and 11 switch the counter output and the top seven bits of U9 - latched from the data bus when DMASTART was written - to the memory address bus to give the target address.
At the same time, the CF address is tied to zero, and it's ~RD and ~WR input are replace with a locally generated signal - ICs 1,3, and 4 and a modified signal replaces system R/~W.
Before starting the DMA, the processor writes the LBA to the CF, starts the transfer, and waits until the CF is ready to transfer. Then it writes the DMASTART; the low bit of the page address defines whether this is a CF-RAM or RAM-CF transfer.
For writes to the CF, R/~W stays high to read memory, and ~WR pulses once per clock to force the CF write. ~RD stays high. To read, ~WR stays high and R/~W pulses low once per clock, along with ~RD. I _think_ that gives me a valid transfer time at 1.8MHz; the data appears some time after ~RD goes low and is written to RAM on the rising edge.
At the end of the transfer, the timers stop, the flip-flop resets, BE is raised and RDY deasserted. The processor starts and has the data available from the next instruction.
I hope...
Neil