Hi everyone it has been a while. I have updated the schematics of my computer. And ordered pcb's but unfortunately my computer does not work.
When I push the reset button I don't get what I expect I used Ben Eaters Arduino program to debug the output. I expect to see the reset vector (fffc, fffd) but I don't see it anywhere:
0111111111111111 00000000 7fff r 00 ; RESET
1010010000000001 00001111 a401 r 0f
0010010000000001 01011011 2401 r 5b
1100010000000001 01010101 c401 r 55
0110010000000001 00110011 6401 r 33
1010010000000001 00001111 a401 r 0f
0010010000000001 01010011 2401 r 53
I must be doing something wrong but I'm out of ideas. Perhaps someone can do a review of my schematic? If you see any mistakes I'm eager to hear it!
Thanks!
My 6502 computer
Re: My 6502 computer
- Attachments
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- ViridiComputer.pdf
- Schematic
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Re: My 6502 computer
I skimmed through the schematic, and nothing jumped out at me. The logic symbol for your address decoder looks unfamiliar, but I assumed it was a NAND gate.
My first thought is that the initial address is generated by the 6502, as the rest of the IC's aren't involved. If the first address on the bus doesn't look correct, then you need to start with the CPU and its connections to the system.
I would enter full paranoid mode and assume either a trace wiring error, bad solder joints, or debug tool malfunction. With the board powered off and my DMM in connectivity testing mode. I would validate the connections of all the address and data bus pins. I would also double check the connections of the debug tool you are using to make sure they're correct too.
If everything checks out, then I would test the debug tool separately to make sure it can read addresses correctly.
My first thought is that the initial address is generated by the 6502, as the rest of the IC's aren't involved. If the first address on the bus doesn't look correct, then you need to start with the CPU and its connections to the system.
I would enter full paranoid mode and assume either a trace wiring error, bad solder joints, or debug tool malfunction. With the board powered off and my DMM in connectivity testing mode. I would validate the connections of all the address and data bus pins. I would also double check the connections of the debug tool you are using to make sure they're correct too.
If everything checks out, then I would test the debug tool separately to make sure it can read addresses correctly.
Last edited by Martin_H on Sun Feb 01, 2026 4:03 pm, edited 1 time in total.
Re: My 6502 computer
Your address decoding seems fine; it's identical to my current hobby computer! Your clock gating for the RAM is a little strange, but that shouldn't stop you from loading the reset vector from ROM. Your first check should probably be that all the annoying Dupont cables connecting to your Arduino are hooked up and attached to the right pins.
"The key is not to let the hardware sense any fear." - Radical Brad
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BigDumbDinosaur
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Re: My 65C02 computer
Did you perchance forget to terminate SOB (pin 38) on the 65C02? Your “schematic” shows that it is floating, which is a no-no on almost all CMOS devices. Unless you plan to use SOB for something, you need to pull it up to VCC.
The reason for me quoting the word “schematic” in the above sentence is your drawing borders on the unreadable for me—and, yes, this is meant to be a point of criticism.
Mostly what you have is a bunch of boxes with netlist tags hanging off of them, which, to me, conveys little about what the circuit is supposed to be doing. Also, despite the well-meaning intentions of IEC 60617-12:1997 (the standard that pushes the rectangle mess), gates are better drawn with logic symbols as defined by IEEE 91/91a-1991; such symbols are routinely published in data sheets because they have been in use in digital circuit design for over 50 years.
Using the IEEE 91/91a-1991 symbols quickly conveys to the reader what the device does; a box with nothing but an ampersand in the middle is confusing...does that represent an AND gate or did you fat-finger the keyboard while labeling your parts?
Confusingly, parts of your drawing have gates drawn as logic symbols and other parts drawn with rectangles. Although I think the IEC 60617-12:1997 standard is inferior in schematics, you should pick one standard and stick to it.
Netlist tags should, if possible, only be used to indicate connections that go to another page in the schematic. Using netlist tags to indicate on-page connections makes the reader have to search the page to find every instance of that tag, which, for me at least, impedes visualization of the circuit.
In drawing a computer schematic, I try to separate various parts of the circuit according to their basic functions. For example, I devote one page to the MPU interface, a different page to RAM and ROM, yet another page to I/O and have the “external interface” (outside world connections) on a page of its own. I’ve also started using a separate page for clock generation, since my most recent designs incorporate more complexity into that aspect of the unit than used in previous work.
The first attached schematic is an example of how what I have described looks. The second schematic shows how an entire unit’s circuit can be depicted on an architectural-C drawing (which appears to be the default page size in Kicad; the first schematic is an ANSI-B drawing) with minimal use of netlist tags.
BTW, you have a booby-trap waiting for you in the way you have your ROM hooked up.
Think carefully about what will happen if ROM is selected during a write cycle. While you are at it, you might want to revisit how you are controlling your RAM—gating chip select with the clock is not good design, in my opinion.
Lastly, there is no good reason to use a 74xx132 in this application—the Schmitt action is unnecessary.
The reason for me quoting the word “schematic” in the above sentence is your drawing borders on the unreadable for me—and, yes, this is meant to be a point of criticism.
Mostly what you have is a bunch of boxes with netlist tags hanging off of them, which, to me, conveys little about what the circuit is supposed to be doing. Also, despite the well-meaning intentions of IEC 60617-12:1997 (the standard that pushes the rectangle mess), gates are better drawn with logic symbols as defined by IEEE 91/91a-1991; such symbols are routinely published in data sheets because they have been in use in digital circuit design for over 50 years.
Using the IEEE 91/91a-1991 symbols quickly conveys to the reader what the device does; a box with nothing but an ampersand in the middle is confusing...does that represent an AND gate or did you fat-finger the keyboard while labeling your parts?
Confusingly, parts of your drawing have gates drawn as logic symbols and other parts drawn with rectangles. Although I think the IEC 60617-12:1997 standard is inferior in schematics, you should pick one standard and stick to it.Netlist tags should, if possible, only be used to indicate connections that go to another page in the schematic. Using netlist tags to indicate on-page connections makes the reader have to search the page to find every instance of that tag, which, for me at least, impedes visualization of the circuit.
In drawing a computer schematic, I try to separate various parts of the circuit according to their basic functions. For example, I devote one page to the MPU interface, a different page to RAM and ROM, yet another page to I/O and have the “external interface” (outside world connections) on a page of its own. I’ve also started using a separate page for clock generation, since my most recent designs incorporate more complexity into that aspect of the unit than used in previous work.
The first attached schematic is an example of how what I have described looks. The second schematic shows how an entire unit’s circuit can be depicted on an architectural-C drawing (which appears to be the default page size in Kicad; the first schematic is an ANSI-B drawing) with minimal use of netlist tags.
BTW, you have a booby-trap waiting for you in the way you have your ROM hooked up.
Think carefully about what will happen if ROM is selected during a write cycle. While you are at it, you might want to revisit how you are controlling your RAM—gating chip select with the clock is not good design, in my opinion.Lastly, there is no good reason to use a 74xx132 in this application—the Schmitt action is unnecessary.
x86? We ain't got no x86. We don't NEED no stinking x86!
Re: My 65C02 computer
BigDumbDinosaur wrote:
Did you perchance forget to terminate SOB (pin 38) on the 65C02? Your “schematic” shows that it is floating, which is a no-no on almost all CMOS devices. Unless you plan to use SOB for something, you need to pull it up to VCC.
BigDumbDinosaur wrote:
The reason for me quoting the word “schematic” in the above sentence is your drawing borders on the unreadable for me—and, yes, this is meant to be a point of criticism.
Mostly what you have is a bunch of boxes with netlist tags hanging off of them, which, to me, conveys little about what the circuit is supposed to be doing. Also, despite the well-meaning intentions of IEC 60617-12:1997 (the standard that pushes the rectangle mess), gates are better drawn with logic symbols as defined by IEEE 91/91a-1991; such symbols are routinely published in data sheets because they have been in use in digital circuit design for over 50 years.
Using the IEEE 91/91a-1991 symbols quickly conveys to the reader what the device does; a box with nothing but an ampersand in the middle is confusing...does that represent an AND gate or did you fat-finger the keyboard while labeling your parts? Confusingly, parts of your drawing have gates drawn as logic symbols and other parts drawn with rectangles. Although I think the IEC 60617-12:1997 standard is inferior in schematics, you should pick one standard and stick to it.
Netlist tags should, if possible, only be used to indicate connections that go to another page in the schematic. Using netlist tags to indicate on-page connections makes the reader have to search the page to find every instance of that tag, which, for me at least, impedes visualization of the circuit.
In drawing a computer schematic, I try to separate various parts of the circuit according to their basic functions. For example, I devote one page to the MPU interface, a different page to RAM and ROM, yet another page to I/O and have the “external interface” (outside world connections) on a page of its own. I’ve also started using a separate page for clock generation, since my most recent designs incorporate more complexity into that aspect of the unit than used in previous work.
The first attached schematic is an example of how what I have described looks. The second schematic shows how an entire unit’s circuit can be depicted on an architectural-C drawing (which appears to be the default page size in Kicad; the first schematic is an ANSI-B drawing) with minimal use of netlist tags.
Mostly what you have is a bunch of boxes with netlist tags hanging off of them, which, to me, conveys little about what the circuit is supposed to be doing. Also, despite the well-meaning intentions of IEC 60617-12:1997 (the standard that pushes the rectangle mess), gates are better drawn with logic symbols as defined by IEEE 91/91a-1991; such symbols are routinely published in data sheets because they have been in use in digital circuit design for over 50 years.
Using the IEEE 91/91a-1991 symbols quickly conveys to the reader what the device does; a box with nothing but an ampersand in the middle is confusing...does that represent an AND gate or did you fat-finger the keyboard while labeling your parts?
Confusingly, parts of your drawing have gates drawn as logic symbols and other parts drawn with rectangles. Although I think the IEC 60617-12:1997 standard is inferior in schematics, you should pick one standard and stick to it.Netlist tags should, if possible, only be used to indicate connections that go to another page in the schematic. Using netlist tags to indicate on-page connections makes the reader have to search the page to find every instance of that tag, which, for me at least, impedes visualization of the circuit.
In drawing a computer schematic, I try to separate various parts of the circuit according to their basic functions. For example, I devote one page to the MPU interface, a different page to RAM and ROM, yet another page to I/O and have the “external interface” (outside world connections) on a page of its own. I’ve also started using a separate page for clock generation, since my most recent designs incorporate more complexity into that aspect of the unit than used in previous work.
The first attached schematic is an example of how what I have described looks. The second schematic shows how an entire unit’s circuit can be depicted on an architectural-C drawing (which appears to be the default page size in Kicad; the first schematic is an ANSI-B drawing) with minimal use of netlist tags.
BigDumbDinosaur wrote:
BTW, you have a booby-trap waiting for you in the way you have your ROM hooked up. Think carefully about what will happen if ROM is selected during a write cycle. While you are at it, you might want to revisit how you are controlling your RAM—gating chip select with the clock is not good design, in my opinion.
Think carefully about what will happen if ROM is selected during a write cycle. While you are at it, you might want to revisit how you are controlling your RAM—gating chip select with the clock is not good design, in my opinion.BigDumbDinosaur wrote:
Lastly, there is no good reason to use a 74xx132 in this application—the Schmitt action is unnecessary.
Well I think I have some work to do. Thanks everyone!
Re: My 6502 computer
@viridi, keep at your computer and coming back for help. I've had many circuit design failures, but the forum has always pulled me though them. You will always learn something along the way and not make that mistake again.
The thrill of a clean reset and your computer running your code is well worth the frustration along the way.
The thrill of a clean reset and your computer running your code is well worth the frustration along the way.
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Re: My 65C02 computer
viridi wrote:
I'm a beginner so there is a lot to learn for me. I agree that the symbols are less readable I used the symbols available in Kicad for the HC variant of the 74 series IC's. Splitting up the schematic in multiple pages sounds like a good idea but I wasn't sure which section to put on which page.
If you're never going to print them, or if you can print them small enough to get on whatever size of printer you have and still be able to read things, I would recommend putting everything on one page, unless there are separate plug-in modules for example which could go on another page. At a consulting job I did a few years ago, they had this big circuit on lots of pages, and I spent the first 38 hours (!) looking for matching tags and writing the page number and the coordinates (like H4 for example) to be able to find them more quickly in subsequent steps. It cost the company dearly, as they were paying me $100 an hour! Such a drawing habit was a disaster though. It makes it a lot easier to follow if all the related stuff is on one page, and all the connections are drawn in, rather than having what amounts to a netlist written around boxes. The latter can be followed ok by board-layout software, but not by humans. I have an example of an all-on-one-page basic whole computer schematic near the top of the page at http://wilsonminesco.com/6502primer/potpourri.html . The whole thing fits neatly on my monitor all at once. There are things about every single schematic-capture software I've evaluated that I don't like; so I still do my schematics by hand.
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
Re: My 65C02 computer
viridi wrote:
I'm a beginner so there is a lot to learn for me. I agree that the symbols are less readable I used the symbols available in Kicad for the HC variant of the 74 series IC's.
- You don't need to select the exact component you actually intend to use for the schematic. For a logic function, you can choose e.g. a 7400, 74F00, 74HC00... whatever. If it has the same pinout as the part you will use, the schematic will convert to a PCB correctly (though using it in the circuit simulator may not; that's a different problem that I know nothing about).
You might, for example, select and place a 74LSxx part when you need a 74HCxx, but the HC part isn't available in the symbol library. Once it's on your diagram, all you need to do is rename it - click on the name to edit. If it's a multi-gate part, all the gates, and the power connector, will change with one click.
So you don't need to use a symbol you don't like. Of course, the 'proper' way to do it would be to make a new symbol, but I won't go there... - Kicad drawing surrounds default to A4. That's handy, because most printers (at least in the metric side of the world) are filled with A4. But you can change the size of that surround at any time, without affecting its contents, in File/Page Settings. It just replaces the existing surround with one of the new size.
My default (Linux) printer driver optionally fits a drawing to the printer, so e.g. an A3 drawing is shrunk to fit. Things appear about 0.7 times as large as they would be on a larger print, so they're still usually readable. So I will often use A3 (or sometimes A2) as my page size. I find that an A4 frame has room only for one or two larger chips and can make things untidy trying to squeeze things in.