Note: I've updated the web page with a new version, the one I am currently testing, including VHDL (which is much more readable than before and I now understand it completely (I think ;-))

http://www.6502.org/users/andre/cbmhw/pet816/index.html

More explanations and tests to follow.

André

You mentioned that the 512K SRAM is through-hole. Do you have apart number for it? What's the access time on it?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

The same one as mentioned here viewtopic.php?t=1600 with 55ns access time

BTW: I shot myself in the foot with the published 1.5 VHDL version. Expect an update over the weekend...

André

Another update. The board just passed the benchmark on 1MHz (Both, PET8296 and CS/A65 with MMU board), and 2MHz (CS/A65 with MMU board). And the burn in already runs for about half an hour at 10MHz in the PET :-)

This one was really one of the meaner parts, almost as mean as my trouble with DRAM... OTOH I learned a lot about VHDL... I think I should now just switch it off until I have my website updated, and not switch it on for a while ;-)

I'll update the web site with in-depth explanations of the board this week (I hope. I know I've said so before...- hey, it's a hobby :-)

Cheers,
André

Finally, finally, finally ....

All info you want on that 65816 board...:
http://www.6502.org/users/andre/adv65/pet816/index.html

Enjoy!

André

Now the board not only runs on my 2MHz CS/A board and the 8296 PET, but also on a dynamic 9" non-CRTC PET 4032 :-)

I actually use it to debug the PET 4032, as there seems to be a problem with the RAM. I put the original ROMs into the 65816 board's ROM, plus some boot setup code, now the CPU runs completely on the 65816 board (all in fast RAM), only I/O is used from the main system. The I/O works, so I can now even load debug code from the disk drive and find out what's wrong with the 4032.

http://www.flickr.com/photos/afachat/4961310278/
http://www.flickr.com/photos/afachat/4960705675/

André

Excellent result - well done. (I've got a Beeb with flaky RAM and we have a similar trick with our board to use only fast onboard RAM. This is a good story for giving old hardware a new lease of life.) I'm sure you're doing better than we are though!

Which reminds me, I don't think I ever did take a look at your sources.

Cheers
Ed

Thanks :-)

I also wrote an extensive article now on how it actually works, with timing diagrams etc.

http://www.6502.org/users/andre/adv65/pet816/works.html

Hope it helps

André

Andre, this is awesome work. I personally would have used the RDY approach, but I can also see how this technique works as well. The 65xx architecture is, internally, simple enough to think of the clock input as an asynchronous, externally controlled signal.

I don't think this technique would fly with most other CPU architectures. It certainly wouldn't fly with an AVR, since numerous on-board peripherals depend on a single clock feed. Of course, this probably rules out the 65265 and 65134 as well.

Now, I have to wonder if my design concepts a high-speed backplane for a 65xx system have been backwards. Instead of the backplane or CPU driving the bus clock, perhaps each individual peripheral should drive its own clock, and let a motherboard-resident arbiter deal with clock synchronization. If you can deal with the jitter, it seems like the least-hardware, least-cost solution.

Reading... Work much appreciated! Reading...

Jeez, now I know, I too have to learn VHDL(or Verilog). I couldn't make timing delays like you said you did on your 5ns delay, using my schematic only method of programming an FPGA. The ISE software sees the delay and optimizes it out. I'm sure I could change some settings/multiple settings in multiple various menus to achieve what could be done in one command under VHDL/Verilog control. I'm starting to understand the power of VHDL/Verilog.

But how long have you really been experimenting with the language/s Andre?

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

The timing delay is only for simulation. The CPLD does not have any delay lines...



Since about beginning of this year IIRC. My first board using VHDL on a CPLD was the 65816 CS/A CPU board, but I did not simulate anything, just basically copied the exiting discrete logic schematics into VHDL (not into schematics, into real code). That was a nice learning experience.

I only found out about the timing simulation recently though.

André