6502 Databus Buffering

river · Post by **river** » Fri Dec 05, 2003 6:16 am

Hi,
I'm trying to expand an AIM65 with some extra memory and IO. I am prototyping it on breadboard, which is connected to the AIM65 via its 44pin connector.

I am using a 74LS245 for the databus buffering, but the unit doesn't work with it connected. I tried a few other '245 chips and checked they were okay - and they were. When I remove the '245 and bridge the databus with wires, everything works okay. However, this is fine for testing, but in real life the databus will run out of puff.

I connected the '245 direction pin to the r/w (-ve w) of the 6502. I connected the enable of the '245 to gnd. I tried inverting the r/w, I tried swapping this and swapping that and to no avail. All signals are strong and healthy and well within the limits of TTL.

I know the '245 chips are okay. And, although I have never seen such a circuit, I assume the 6502 can have its databus buffered.

Any ideas on this one?

rgds,
river

jdeboy · Post by **jdeboy** » Fri Dec 05, 2003 6:48 am

Hi River,

try to use the inverted PHI2 bus signal to enable the 245. It may be, that enabling the buffer permanently is responsible for the problem. The 6502 commnunicates just in Phase 2 with external devices.

Joachim

GARTHWILSON · Post by **GARTHWILSON** » Fri Dec 05, 2003 6:57 am

Without more info to know for sure exactly how you're doing it, I'll make a couple of comments.

If you have the E\ inputs of the 245 grounded, then the processor side of it will be driving the processor's data bus anytime R/W\ is up, which is most of the time. That would cause bus contention when the processor is trying to read memory or a 6522 or something like that which would be trying to put data on the bus at the same time. The E\ input will have to be tied into the address-decode logic in order to remedy the problem.

> When I remove the '245 and bridge the databus with wires, everything
> works okay. However, this is fine for testing, but in real life the databus
> will run out of puff.

If you use CMOS parts (or even NMOS), the only fan-out limit is capacitive loading. IOW, if you hold the speed down low enough, one output can drive a nearly infinite number of CMOS inputs. At the AIM-65's 1MHz, capacitive loading should not be any problem with reasonable construction. Instead of using 74LS, I would use 74HCT. The "T" means the thresholds are 100% TTL-compatible.

river · Post by **river** » Sat Dec 06, 2003 5:48 am

Hi,

I tried the invert PHI2, but to no avail. So, I just bridged the databus straight through and its working, so I'll see how it goes. I'd like to see a circuit of one, though.

rgds
Shane

bogax · Post by **bogax** » Sat Dec 06, 2003 7:39 am

"I tried the invert PHI2, but to no avail."

I think you've missed the point Garth Wilson was making.

You've got a board with (presumably) some ROM and RAM
and IO and stuff on a bus (and the processor of course)
and now you want to add a 245 to the bus.

from your description:

"I connected the '245 direction pin to the r/w (-ve w) of the 6502.
I connected the enable of the '245 to gnd."

you've rigged it so that ANY TIME the processor does a read
the 245 will try to drive the bus.

So if the processor trys to read an instruction from ROM
(for example) the ROM will try to drive data on to the bus
and the 245 will also try to drive data onto the bus because
you're doing a read.
They'll be fighting it out ("bus contention") and presumably*
you'll get garbage on the bus not an instruction.

So you need some address decoding to enable the 245 for reading
only when you intend to read it and disable it when your trying to
read something else on the bus

*unless the ROM wins, which is unlikely since the 245 is designed
specifically to have lots of drive (which, I suppose, is one reason
you chose it),
or by some quirk of fate or design they happen to be trying to
drive the same data onto the bus.

river · Post by **river** » Sat Dec 06, 2003 11:34 am

Hi,

Yes, I got the point..... finally.

As I am adding components within the address range of 0000h to 9fffh, I must ensure that the 245 is enabled only when this address range is active. Outside of this range is the on-board AIM65 devices and therefore the 245 should be disabled when addressing this part of memory.

If the 245 is permanently active it will deliver information onto the databus, even when accessing on-board AIM-specific components. This is an issue I must address (no pun intended).

Okay... am I on the right track now?

rgds
river

bogax · Post by **bogax** » Sat Dec 06, 2003 4:37 pm

"Okay... am I on the right track now?"

Yes, except..

"I am adding components within the address range of 0000h to 9fffh,"

Zero page, 0000h - 00FFh, has special uses and the stack is at
0100h - 01FFh.

So the board probably has some RAM in those ranges at least.
(but I'm not familiar with AIM)

river · Post by **river** » Sat Dec 06, 2003 11:32 pm

Hi,

I have removed the on-board 4K RAM of the AIM65, and all RAM is now with the 32K (62256) chip, which is part of the expansion I am building. The system boots and I ran some memory tests to prove its okay.

The AIM monitor memory and IO devices and ROMs reside in address range A000-FFFF.

Hey, thanks you guys for the help. I couldn't see the trees for the forest. Much appreciated.

rgds
river

river · Post by **river** » Sun Sep 27, 2009 10:09 pm

Hi,

Crikey, it's been a long time since I posted here. Life has been hectic and I haven't been able to get back to my old processor systems for sometime, but hopefully this will soon change.

In regards to my AIM-65s - I modified one of them to provide extra capacity. It now has 40k RAM (1 x 32k and 1 x 8K) Chips (which means I removed the on-board 2114 chip RAM). It has an extra 6522 (as well as the existing user 6522), two 6551 ACIAs, 6840 Timer/Counter and (just for the hell of it) an 8255 PPI.

I've built a box for it and have routed all the I/O ports to the top where I have attached a few breadboards. This helps when developing 'cos I can breadboard/protoytpe quickly and easily.

I have built an 8085 development system in a similar manner, where it has 48K RAM and various I/O chips which are routed to breadboard for easy development. I am building an EPROM programmer at the moment, and not sure whether to use the 8085 or the 6502 system to do the initial hardware and software. Whatever system I use, once completed, I will build as a dedicated EPROM burner. Fortunately I have ample supplies of processors, peripherals and memory chips for the 8080/85 and 6502/6800 chips.

Oh, couple of years ago I got my hands on a bunch of old SC/MP chips and built a small system with one of them. Also got some 2650 chips a year ago and will be doing something with them too... when I get the time.

seeyuzz
river