Placed an order for the boards. Made this one a 32K one to keep complexity down and also making it able to reuse my existing components. If all (or even some) of the concepts I want experiment with work out well, I'll make a bigger better version later on.
What is U2? Is that the FPGA you mentioned a few posts ago? I see what looks like a QFP package. Are you able to solder that?
Yeah, thankfully my soldering is fairly reasonable. While not the most fun thing to hand solder, this is the typical outcome from my previous efforts. Fairly traumatising at the time, but worth it.
Parts are here and assembly has begun. I've soldered the extremely nasty components and am testing as I go. So far so good!
Quite happy with how clean the clock has come out, measured at where the PHI2 input will be at the 6502. Very clean, no ringing, and a 3.7nS rise/fall time.
So far so good. Two chip design, executing a routine to fill 256 characters between A & B. Running at a modest 18.8 MHz at 3.3v. I'm sure it will clock higher but the next jump is 37.6 MHz, which is a bit much at 3.3v (I know, I tried it. ).
Great job! I know W65C02 can run 25Mhz at 3.3V, but 37mhz is probably too fast. Are you able to change the duty cycle of clock? Longer high phase of clock may help.
Bill
So far so good. Two chip design, executing a routine to fill 256 characters between A & B. Running at a modest 18.8 MHz at 3.3v. I'm sure it will clock higher but the next jump is 37.6 MHz, which is a bit much at 3.3v (I know, I tried it. ).
What are we seeing? The screen looks almost black to me. Is it perchance mostly blue?
Yep, blue on blue. Will change the colour scheme on the next run, as I remember you are “colour challenged”. Don’t worry, I’m starting to become “vision challenged” overall. Some of this soldering wasn’t fun at all. Hehe!
@Plasmo - Yeah, I plan on changing the stretching to accomodate a wider range of clock frequencies. The base clock is 74.5MHz as I am targeting a 1080P video mode down sized to a quarter of that.
Yep, blue on blue. Will change the colour scheme on the next run, as I remember you are “colour challenged”.
Ah-so...explains what I am not seeing.
Quote:
Don’t worry, I’m starting to become “vision challenged” overall. Some of this soldering wasn’t fun at all. Hehe!
I feel your pain with the soldering aspect. My vision has deteriorated to where 100-mill centers look as daunting as the pin pitch of QFP packages looked 20 years ago. I have a new POC design on the “drawing board,” but haven’t moved ahead with it because I don’t think I can actually build it.
plasmo wrote:
Great job! I know W65C02 can run 25Mhz at 3.3V, but 37mhz is probably too fast.
Interesting how the 0.6µ TSMC 65C02s can be run so fast, and that production testing is done at 20 MHz, the latter which suggests to me the powers-that-be at WDC know the product’s capabilities are much better than back when they were produced with 0.8µ Sanyo dice. Yet the data sheet stubbornly insists that 14 MHz is the clock ceiling (other than what is hinted in the FMAX vs VDD curve) and continues to list the same timing values that were published in data sheets from a quarter-century ago.
The letters look mangled at this speed, but they are fine. I haven't added any form of vSync testing yet, so they are getting overridden mid raster.
Had a quick attempt at some clock stretching but I couldn't get it as granular as I was hoping (not at 6 am in the morning anyway ). Will rethink how I'll approach that later on, so ~18.8 MHz is it for the moment. Will probably look at some boolean approaches later on.
I have a new POC design on the “drawing board,” but haven’t moved ahead with it because I don’t think I can actually build it.