An Improved MENSCH™ Microcomputer

[Martin_H]

@George and Neil, thanks for the help with the flip function. Relocating the decoupling and oscillator loading caps to the underside of the board saved a ton of space. I also changed the voltage regulator to the LM1117, put it on the underside of the board, and changed the capacitor values to match it.

That opened up space for a PCB mount slide switch. But there are no footprints for slide switches in the default library! I will hold for now, as I need to focus on making the QFP footprint amenable to hand soldering.

I also added a R/W header control reader for the EEPROM. My 6502 SBC has that as it allows for updating the EEPROM from the SBC itself, although I will admit to never using that feature.

@ Jeff, point taken about keeping voltages above Vcc off the board. That would save space and avoid a potential headache. My 6502 SBC is a PCB that I got from Rich Cini and he used a USB jack for power, probably for that reason.

I am getting close to running traces between the components, which I imagine will be a significant challenge and learning curve.

[barnacle]

Between SOIC or SOP legs, there is no problem with 0.2mm trace width, but you can't go between the legs on a QFP as a general rule. If there isn't space to meet the preset constraints, Kicad won't let you route in that direction

Here's a SOP-28 sitting inside a DIP-28 and sharing all the signals, with a second similar arrangement to the right (all but a couple of signals are shared). Traces are 0.2mm, vias 0.6mm/0.3mm holes.

Neil

Edit: DIP pin centres = 2.54mm; SOIC/SOP pad centres 1.27mm; QFP pad centres (usually) 0.65mm/0.5mm

[Martin_H]

It was a learning curve, but I figured out the footprint editor. I started with the PQFP-100_14x20mm_P0.65mm, created a project local version called Mench Reloaded_footprints:PQFP-100_14x20mm_P0.65mm_HandSolder, and lengthened the pads and bounding lines. I laid the new version on top of the old version to ensure the pad positions and pitch were unchanged, only their length beyond the pins increased by 0.75mm.

@Neil, so you're suggesting I add a second SMD RAM to the schematic and nest it inside the existing RAM. That way someone can choose between RAM styles? The DIP 128K SRAM is available at Mouser for $5.80 and doesn't say it's obsolete. But it's also available in SOP-32 for $4.20.

Which brings me to some questions.

Do I need to create hand solder versions of the SOIC-14 and SOP-32 footprints as well?

Or is it only for the QFP-100 because the pin pitch is so fine?

Rather than go with two SRAM footprints, would it be better to just go with the SOP-32 AS6C2008A which is 256K?

[barnacle]

It was purely a suggestion to give options to a future builder. As a simple matter of economics, I've noticed that in general, smaller footprint components are cheaper than DIPs as a general rule, but DIPs are a _lot_ easier to work with for both testing and fitting (you can e.g. hang probes on DIP legs which is trickier for SOP/SOIC).

SOIC and SOP will both fit inside the 0.6" DIP footprint; SOIC parts will fit on SOP footprints but the other way around only with difficulty - the SOP pins are slightly wider than the SOIC and overlap the SOP pads a fraction.

The way I did it was not to add a second component to the schematic - that way works, but the rule checker sulks about things inside other things - but rather to select 'add a footprint' (from the menubar on the right) and select the SOP footprint there. Place it inside the DIP footprint so it doesn't touch any of the pads there, which works if you select the centre of the part - the little purple cross - and then M to move it over the centre mark of the DIP. I used an 0.0125"/0.3175mm grid, which I added as a custom grid.

Then you need to select each pin on the SOP in turn, right click for properties, and give the pin the same signal name as that of the DIP. If you zoom in enough you can see the signal names. As you name them, Kicad will add rat's nest connections between the pins.

But that is of course entirely optional; I make it only as a suggestion. Obviously you'll fit only one or the other...

As a practical matter, were I doing the layout routing, I would start first with the parallel connections between the ram and rom, and then the connections from there to the processor and the VIA. But that's maybe just me.

I don't think you'll need to alter the SOIC-14/16 parts to solder them; just start by getting one corner down, then the diagonally opposite one, and use lots of flux.

Neil

[Martin_H]

Neil, adding a SOP part layout is a good idea, and your description of the process was helpful. But I have enough of a challenge with wiring the current layout, so I will save it for a future project.

I will take your advice and wire the RAM and EEPROM tracks first. My plan is to lay vertical tracks on the top layer, and horizontal tracks on the bottom one. All power tracks will be on the bottom, as it should be easy to reach all IC's, except the SMD components. I will use vias to reach the power pins of the SMD components.

I figured out how to use the design rules to automatically set track widths. For the power rails I will use 0.5mm tracks and, for address, data, and control signal tracks I will use 0.2mm, vias 0.6mm/0.3mm holes like your design.

[Martin_H]

I've begun routing the tracks and any comments on what I'm doing wrong before I duplicate it many times over would be helpful.

Things I think I'm doing right:

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* The vertical traces between the EEPROM and RAM.
* The tracks for the decoupling capacitors under the IC's.
* The VIA port wiring tracks look reasonable to me.

Things that look not so great:

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* The traces around the XBUS at the top are starting to look iffy.
* I deleted the horizontal d0..3 traces to the XBUS because the corners looked too sharp to me.
* The address bus traces off the 65c265 started out okay but started to concern me.
* The routing tool seems to have a mind of its own and seems to fight me.

[gfoot]

Martin_H wrote:

* I deleted the horizontal d0..3 traces to the XBUS because the corners looked too sharp to me.

Sharp corners are considered poor style but don't really matter much these days, so don't worry about them.

Quote:

* The routing tool seems to have a mind of its own and seems to fight me.

That's what it's best at. Did you discover what "D" and "/" do yet? They can be very useful. Also get used to the fact that clicking locks the track in place a bit at a time, and you get used to how much is getting locked with each click. There's also Backspace to unpin the last "click" which can be handy.

(I'm saying this from memory as this is all muscle-memory in practice, so apologies if any of the keys are wrong!)

One other thing - you can opt to have the ratsnest drawn using curvy lines, which I find easier to follow as it reduces the times where a line goes through a pad without actually meaning to connect to it.

Oh, yet another thing - is this a 2-layer or 4-layer board? If it's 4-layer then you can immediately set up a ground plane and maybe a power plane, and some of the ratsnest will disappear as those pins will automatically be connected through these.

Moving the RAM closer to the ROM and moving them both to the right a bit may make the routing to XBUS easier. Note that it doesn't matter what order the address and data pins are wired on the RAM so if it helps your routing, you can change them in the schematic. Matching the ROM has some advantages but there's acres of space under these chips in which you can swap traces around if it helps you, while the space between RAM and XBUS is really tight.

[barnacle]

Also, you might find the 'K' key useful to toggle drawing filled traces, rather than the outlines you have.

I - and many others - find it handy to draw up/down traces on one side, and left/right on the other. In your case that would be up/down on top... it means you can (nearly!) always get somewhere without getting blocked by other traces. Again, personal preference (but you'll see what I mean in the picture a couple of responses ago).

And I echo gfoot's comment about moving the ram closer to the rom (though I prefer not to mess around with address and data lines; I've done that on a commercial product (by instruction) and found hardware bugging was confusing. But it works.

I suspect I may be not the only one wanting to get their hands on your Kicad project to see what we can do with it

Neil

[gfoot]

I thought of something else overnight - you're using a DS1813 but you don't have a pull-up on the reset line, it's true that it's not recommended by the datasheet but as BDD has advised in the past, you might find you need one - I have also run into this, and initially assumed by DS1813 was faulty until I remembered that advice. So you might want to put a footprint on the board for a pull-up resistor, even if you don't end up populating that component in the end.

[BigDumbDinosaur]

gfoot wrote:

I thought of something else overnight - you're using a DS1813 but you don't have a pull-up on the reset line, it's true that it's not recommended by the datasheet but as BDD has advised in the past, you might find you need one - I have also run into this, and initially assumed by DS1813 was faulty until I remembered that advice. So you might want to put a footprint on the board for a pull-up resistor, even if you don't end up populating that component in the end.

Yep!

The DS1813’s internal pull-up is weak and if solely relied upon, may make the reset circuit susceptible to noise.  I use 3.3K for the pull-up.

[Martin_H]

Thanks for the warning about the need for a pull up on the DS1813.

Attached is an image of my progress so far. I moved the RAM closer to the ROM and redid those lines. The additional space around the XBUS made it possible to route the address, data, and csb lines. It looks like I'm at least half done. I find that I make progress, then have to undo some work because I box myself in, but I figure out a better way to do what I just did. Redo and then move forward. I'm hoping I'm learning something along the way that will improve my future work.

But I am starting to run out of space again. I am contemplating ditching the onboard power supply and have power header. The additional space would come in really handy right now.

Questions:

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* Several times I accidentally made something called a micro via instead of a regular via. I redid it as a regular via. But are micro vias useful?
* This is a two-layer board. Can I turn it into a four-layer board? Are those layers just for ground and power?
* Several of the w65c265 pins are no connect. Can I use those pads to route traces? Or is that a bad idea?
* I am using a pull up on the RAM CS2 line because it is supposed to be high. Is this needed, or can it be wired directly to +5V? 

[gilhad]

As I see it, I wonder if rotating the CPU 90 degrees counterclockwise would not result in shorter and more straight traces?

Also, is it possible to swap the J4 and J6 connectors?

Also, I would remove some vias near the XBUS connector and let the routes end on the other side of the pins.

I think that it can be converted into a 4-layer layout and that the internal layers may contain any traces, not just power. But having power there makes better shielding against noise.

(I would try it on a separate copy of this project, so if it would not help, it could be easily reverted back / ignored.)

I think that generally connecting no-connect pins is not a good idea, as they may be used for any internal purposes, such as testing, but I do not know whether it is the case with this particular chip.

[barnacle]

If a pin is marked no-connect, to not connect it to anything except a disconnected pad. Don't try and use it for routing, you _must_ go around it.

Are you wedded to the exact position of the xbus socket? I note it's ever-so-slightly not quite on the same grid as the memories, which isn't a show stopper but upsets my PCBOCD (I grabbed the project from your github repository from a few days ago, so it isn't currently up to date).

Remember you have space for three or four tracks above the xbus socket, and two or three in the middle, running left-right!

Neil

[gfoot]

Sometimes for NC pins I have edited the footprint and deleted the pad and through-hole so that I could route more tracks through it. I then cut off the socket pin. If you're not using a socket then you could probably still bend or cut the IC pin, obviously it damages the IC but you were going to solder it to the board anyway with that pin not used so maybe that's OK. And obviously this only works for hand-assembly!

You can change the "stack up" of your project for sure, I don't recall exactly how, something like PCB Properties though. There are shortcut keys for selecting layers - Page Up and Page Down for the outer layers, I don't recall for the inner layers though as I've not finished any 4-layer boards. It might be some of the F-keys.

If you want a layer to be power or ground you have to manually set up a "fill zone" on that layer - and note that when you move components or board edges around, you need to press "B" (I think) to make it refill all zones, as they don't update dynamically. Fill zones automatically join to things that are in the same net (pads and traces), and leave an exclusion zone around things that are not, and they also make special patterns around pads to avoid too much thermal sinking (which would make soldering harder).

I wouldn't worry about having a layer dedicated to a power plane - you can use the third layer for normal traces when you need to - perhaps for special cases where your horizontal/vertical layers have done as much as they can and you still have a few other signals to route on top. But it may be beneficial to route all the power connections on this plane before using it for anything else, as there are a lot of power connections and they go to all devices. You can reroute them (drag with "D" for example) if it turns out later that they are in the way but you don't want to get stuck in a situation where you can't get power to a device. You could then fill the rest of the layer with power if you like, and this will merge with the hand-mapped traces as they are in the same net.

For vias, I usually just start laying the trace on whichever layer I want, then press "V" while still laying the trace to make it insert a via and automatically continue laying the ongoing trace on the other side. It is very convenient and gets quite fluid. I don't know how you're inserting microvias, I've never used them.

You can also move certain things in bulk from one layer to another - so if you've carefully routed some traces but decide you'd rather they were all on another layer, select the traces, go to their properties, and you can edit which layer they are on. The same goes for silkscreen, and fill zones, but I think you need to do each type of thing separately, not all together.

I find I often do go back and redo things, even if I spent quite a long time on them the first time. Often the second or third time is much faster with much better results. It makes you think, it's probably not worth spending as much time on your first pass! I have the same thing with schematic layouts, you can spend ages trying to make them as clear as you can, but sometimes you just need to redo part of it.

[plasmo]

I’m surprised with last several posts about manual routing. Some proficient with manual routing is good, but surely most projects were done with auto router? Perhaps a bit of final touch up with manual routing. I’m not familiar with KiCad, but surely in 2025 it has a capable autorouter that can finish the board in a minute or two? The auto router in my 25-year old tool is fast enough to help me with component placement; I move/rotate components to reduce the efforts for the auto router.
Bill