Help with reading NAND chips on a breadboard

[barnacle]

WCMiller wrote:

Oh, to be clear I meant deciding between using (all) CMOS or TTL. Mixing them would be well beyond my ken.

Keeping to a single logic family ensures that the logic will work. The problem is that not everything on your (anybody's) design is strictly a given logic family. Consider: you will need at a minimum a processor, some RAM, some PROM, and some glue logic.

Let's choose - ignoring ram for now - a W65C02 processor, a 74HC00 and a 74HCT00 for glue logic (other parts in the same families have very similar values), and your SST39SF020A.

Some of this data is extrapolated; it's not directly specified for the 5v Vcc for the HC and HCT parts, for example, and neither does the 65C02 specify its output levels beyond 'CMOS'.

Looking at the first two columns: the first is the level below which the input voltage must be to guarantee a low is understood by the part; the second is the maximum guaranteed low voltage output. Every part has a low output which is lower than every other components maximum permitted low input, so there are absolutely no problems there.

The second two columns tell a different story. Here we have the minimum output level for a high, and the minimum level required to guarantee its correct input. We see that all the families except the ROM have outputs that are close to the rail, well above the voltages required by all the parts. But the ROM only outputs 2.4v... that is insufficient to drive either the processor, or normal HC logic, though it's quite happy talking to itself (naturally) or to HCT logic.

The blunt answer is: it won't work.

The more nuanced answer is: it probably will. But it might not, and if it doesn't, you're out of luck. In spite of the minima for output levels, they're the minima at particular currents; in the case of the ROM it's significantly greater than the input current of a CMOS part. You can expect, in most cases, that the output will be plenty to drive the processor's inputs directly - but you would _never_ design a production part like that. One approach would be to use an HCT buffer between the ROM's output pins and the data bus which would provide a level conversion (at the cost of a few nanoseconds' delay).

I have ignored other issues here: output rise and fall times, required input rise and fall times for example. Also absolute minimum and maximum voltages. Always read the datasheet.

Neil

(true story: at a previous employer, we had a particular logic part which was powered directly from a Vbatt rail. The battery voltage of four new alkaline cells is 6.4V, dropping with time. The part had a Vcc (max) of 7v; every other maker of the similar part offered only 6.5v or 6v. The maker of the part we specified moved their foundry to a new country and thereafter certified the part only to 6.5v... we ended up buying a couple of million of the old parts, and completely redesigning the circuit for the next generation product.)

[JohanFr]

barnacle wrote:

The blunt answer is: it won't work.

The more nuanced answer is: it probably will. But it might not, and if it doesn't, you're out of luck. In spite of the minima for output levels, they're the minima at particular currents; in the case of the ROM it's significantly greater than the input current of a CMOS part. You can expect, in most cases, that the output will be plenty to drive the processor's inputs directly - but you would _never_ design a production part like that. One approach would be to use an HCT buffer between the ROM's output pins and the data bus which would provide a level conversion (at the cost of a few nanoseconds' delay).

Sorry if I am repeating what you just said, but I light bulb went on in my head and now I am confused. So according to the 65C02 sheet, the minimum high level for the data lines should be VDD x 0.7 (3.5V in the case of 5V power rails). But both EEPROMs (28c256) and Flash (SST39SFxx) have a min high output of 2.4V . Wouldn't that mean that all example 65C02 designs all over the web works just by pure coincidence? I.e if I am to rely on the output from ROMs or flash I should buffer it with some HCT logic?

Again you probably just explained it but my brain went into overdrive and I can't comprehend nuances at the moment

[BigEd]

To understand signalling between families, you need to understand that what the inputs will accept, reliably, is one thing, and what the outputs will produce, across all parts and all conditions, is another. Those are the specifications. And then you need to understand that the parts may exceed those specifications. An output high which is for some reason on the low side might nevertheless be sensed as a high by the receiver.

And so you might have a design which works, but is unreliable. Or it works, until it gets hot. Or it works, until you add enough things that the power supply gives a slightly lower voltage. Or it works for you, but when anyone else builds it, it doesn't. Or it works with one brand of memory chips, but not another.

[plasmo]

WCMiller wrote:

Rough schematic. How's that?

There are 3 pages of comments why the original post won’t work and they are valid comments to comply with part data sheets. However, the original post SHOULD work with 2 modifications; 1) tie pins 22 and 24 (CE, OE) to ground instead of VCC, 2) LED will dimly lit, so turn off the light to see them.

Data sheets are very conservative, there are big differences between what are guaranteed to work and what are likely to work.
Bill

[John West]

JohanFr wrote:

Wouldn't that mean that all example 65C02 designs all over the web works just by pure coincidence?

Sort of yes. The numbers in the datasheet are what's guaranteed, over the entire temperature range, with supply voltages anywhere in the specified range, and with whatever load current they're using for testing. And that's for every chip they've sold since the datasheet was published.

There's always some variation in chips when they're made, and they'll be designed so that their typical values are sufficiently far from the guaranteed value that the vast majority of chips pass testing. So almost all of them will be better than needed, and the chances you've got one of the few that aren't are very low. There may have been process improvements since the datasheet was written (there definitely were with the 65C02), and we're working at room temperature with a power supply that's very close to 5V, and much lower load current than the specification requires. That results in output and input ranges that overlap well enough for our one-off builds to work.

If I was selling my designs (or people's lives depended on them), I'd be a lot more careful. If I'm relying on the chips to be 30% better than the specification, and a customer complains that their board isn't working, I can't turn around to the chip manufacturer and complain that their chip is only working as well as they promised it would. But since I'm only building for myself, I can cut corners and rely on it probably working fine.

[Dr Jefyll]

JohanFr wrote:

my brain went into overdrive

I can sympathize. But, broadly speaking, yes -- most example 65C02 designs all over the web work just by pure coincidence... or, more specifically, they work in violation of the specs. And the remedy, if the specs are to be satisfied, is -- as you say -- to buffer the output from the ROMs & flash with some HCT logic. (Or AHCT, or some family with a 'T' in it!)

The reason it's possible to violate the specs has to do with their conservative nature, as others have explained. Just be aware that a WDC project which lacks 'T' buffering and "still works" does so with reduced ability to tolerate electrical noise. (The reduced reliability that results may be tolerable in a hobby environment.)

BTW it's only 65C02's made by WDC which lack TTL compatibility. Other C02's such as those from Rockwell and CMD have inputs which respond reliably to TTL levels, and their specifications reflect this. For a comparison between WDC 65xx chips and those of other manufacturers, see the thread TTL Compatible... NOT! ( modern WDC CPU's ). In particular, check out the animations in the lead post.

-- Jeff

[JohanFr]

I see, thank you all I should definitely probe my SBC to see what levels are ACTUALLY on the board.

Now I will return this thread to its rightful owner, sorry for hijacking it.

[barnacle]

It's that nuanced answer again.

(a) pretty much any CMOS output will drive rail-to-rail _into zero load_. Not all, but most.
(b) any logic input (with the exception of exotica like ECL) will cheerfully operate on a rail-to-rail input. It's the mid-rail stuff that gives it nightmares.
(c) the actual input transition is somewhere around half rail; HCT has a different input arrangement so that it understands TTL input levels
(d) CMOS input stages are generally _very_ high impedance and might require only a few microamps to operate (effectively, you're charging a tiny capacitor).

So TTL nominal outputs will generally be a lot closer to the rail than 2v - stick a scope probe onto the signals on a vintage computer and you'll generally see signals moving up over four or four and a half volts. Which is why you can _usually_ get away with nominal TTL level outputs from RAM and ROM pushing into a CMOS processor.

Going back to the original issue: it seems likely that the current draw through the un-resistored LEDs would cause the output to be below the point at which an LED would light. But I don't know why your bare chip isn't behaving.

Neil

[barnacle]

Dr Jefyll wrote:

BTW it's only 65C02's made by WDC which lack TTL compatibility. Other C02's such as those from Rockwell and CMD have inputs which respond reliably to TTL levels

But sadly, those are the only ones that are available new

Neil

[Dr Jefyll]

Yes, although not everyone insists on buying a chip that's new. Used 65C02's from Rockwell and others do turn up. We even have a thread about various sources for 65xx parts.

And, FWIW, let's note in passing that the inputs of NMOS 65xx parts -- such as plain ol' 6502 (without the 'C') -- are also specified for TTL levels.

-- Jeff

[BillO]

Just noticing in your last schematic that a lot of pins are to be tied to ground. Some breadboards are notorious for having lousy connections. It might be an idea to use a multimeter in continuity mode to ensure all those pins are well connected to pin 16. And/or use the meter on the Vdc function to ensure that none of those pins have any voltage on them WRT pin 16.

[BigDumbDinosaur]

WCMiller wrote:

Oh, to be clear I meant deciding between using (all) CMOS or TTL. Mixing them would be well beyond my ken.

In a new design, there is little-to-no justification for using TTL logic.  Using the latter will reduce fanout, increase power consumption and decrease noise immunity.  Also, if building to run the MPU near FMAX, TTL logic will introduce enough propagation delay to possibly sabotage timing.

For speeds up to around 10 MHz, 74HC logic is fine and will introduce the least amount of switching noise into the circuit.  If you are angling for FMAX, I suggest 74AHC, especially if not building on a PCB.  In my builds, I’ve used 74AC logic, which has more aggressive edges than 74AHC and 74HC—the two logic families have nearly-identical timing characteristics.  74AC , in my opinion, is not a good choice unless you have experience in laying out PCBs for high-speed circuits.  The aggressive edges can cause transmission line effects that may make for instability if the physical layout is not right.

[BigDumbDinosaur]

A factor to be considered is most devices with TTL output levels are able to reach ~3.4 volts if very lightly loaded—however, VOH quickly degrades with load.  Modern WDC MPUs have an transition point around VCC × 0.5 (stated by Bill Mensch and confirmed by Jeff).  That explains why many devices with TTL output levels, e.g., a typical ROM, will function despite seemingly-incompatible logic levels.

For the record, all of my POC units, but one, have been built without data bus transceivers, which means the 65C816 is seeing TTL-level signals.

Dr Jefyll wrote:

BTW it's only 65C02's made by WDC which lack TTL compatibility...

...and that’s only those produced since the conversion to static core was made.  In years past, they did have TTL compatibility.

65c02_1990.pdf

WDC 65C02 Data Sheet (Feb 1990)

(2.32 MiB) Downloaded 69 times

[barnacle]

The last picture in this thread shows what happens when the input voltage is in that gray area between maximum zero voltage and minimum one voltage: viewtopic.php?f=4&t=8393

That's the sort of thing that can spoil your whole day.

Neil

[WCMiller]

BillO wrote:

Just noticing in your last schematic that a lot of pins are to be tied to ground. Some breadboards are notorious for having lousy connections. It might be an idea to use a multimeter in continuity mode to ensure all those pins are well connected to pin 16. And/or use the meter on the Vdc function to ensure that none of those pins have any voltage on them WRT pin 16.

YOU. ARE. A. GENIUS!

I've got it solved; the issue was the A16 pin was plugged into the ground rail, but for some reason it wasn't making connection. I replace the wire with a new one, going to a new hole on the ground rail, and everything started working. I played with some of the lower address wires to go to different addresses, and they output the expected values.

I had been visually checking the wires to make sure they were going to the right rails (I'd gotten THAT confused in the past several times), but I hadn't thought to actually check the signals on them with my multimeter. I will definitely be remembering that as I go forward! Thank you all for your help and your advice; it's been absolutely invaluable, both in regards to the problem I was wrestling with and the more general stuff on logic families and being more diligent about RTFM with regard to datasheets and not making assumptions!