Help understanding PLA decoder

[Phlosioneer]

Hello, I've made CPU simulations before and I've got a working 6502 sim using the function pointer jump table technique. That's no problem. I want to take my emulation and understanding to a lower level now, and implement a PLA-based decoder. I have made decoders for more regular architectures, like pipelined MIPS. But these address modes + the size constraints are stumping me.

From what I've seen online (I think it was 6502visualsim or something?) it has a 5-bit state machine plus 8-bit instruction opcode plus a clock line. I know I'm capable of making a big state machine, so my goal is to instead do something in the same ballpark - 5 or 6 bits. I've made some progress staring at patterns in the 6502 instruction set grid, where the low nibble is the column and the high nibble is the row.

I think I need to split the states into three groups: fetch the operands, then do the operation, then store the results. State chains from each group should be able to be mix-and-matched; every fetch-the-operands state chain ends up in the same final state, then from there it branches into all the do-the-operation states, which converge to a single state, which then branches into all the store-the-results states. But if I do that naively, there's waaaaay too many states, and the cycle timings are all too long. Like a simple AND #$nn would be 6 cycles (common start->load imm->common op start->send AND command->common result start->save to A), but it should only be 2.

Is there a trick or technique I'm missing? Any advice for how to organize it all? Any resources online picking apart the 6502's PLA design?

[rwiker]

Instead of splitting the opcode into nibbles, you might be better off considering grouping into 3+3+2 bits: https://llx.com/Neil/a2/opcodes.html

[leepivonka]

The online 6502 transistor-level simulation is at http://visual6502.org/.
Here is one of many articles: https://www.nesdev.org/wiki/Visual6502w ... ing_States.

A quick summary of the AND # instruction cycles would be:
-- previous instruction is in control --
* Fetch 1st byte of AND #, finish previous instruction
* Fetch 2nd byte of AND #, finish previous instruction
-- AND # instruction gets control --
* Fetch 1st byte of next instruction, A=A and immediate value, update flags
* Fetch 2nd byte of next instruction
-- next instruction gets control --

[BigEd]

See particularly this section of the visual6502 wiki:
https://www.nesdev.org/wiki/Visual6502w ... ime_States

(and, welcome!)

[Phlosioneer]

Thank you all so much, this is exactly what I was looking for! I’ve made good progress now.