Bitslice 6502, is it possible?

[wayfarer]

Could you bitslice the 6502 so its 16d/16a, or 16d/32a ?
i searched and its not really covered. Will it work?
Id think a custom interface instruction decoder on a cpld might be needed, or a lot of glue logic.

[BigEd]

Perhaps see the thread
Index of threads for improved 6502 and derived architectures

[John West]

I don't really understand the question. Bit-slice was an implementation method, in the days when you could get enough transistors onto a chip to make a vertical slice of a computer's ALU and register file, but not the whole CPU. I imagine it would be possible to make something that looks like a 6502 out of bit-slice chips, but they're hard to find these days. And there's little reason to, other than exploring forgotten technologies.

But you seem to be talking about extending the architecture of the 6502 into something else. Of course that's possible. There are many extensions to the 6502 - ranging from just on paper to FPGA to real silicon. My own project started by asking "what if I made the data bus (and thus the contents of each memory location) 16 bits wide?" and following the consequences. I ended up with a processor that's pleasant to use but no longer feels like a 6502. If you want to explore that sort of direction, just sit down and do it.

Or are you talking about using an actual 6502 chip as the slice? That's ringing a bell - I feel someone's asked that before. I won't say it's impossible, but it certainly wouldn't be easy and the results are likely to be ugly. Bit-slices aren't independent and the 6502 doesn't expose the signals you'd need. Addition needs carry in and out of each slice, branches need to combine flags from all slices, and I can't imagine how addresses would work. And the 6502 is of course a complete CPU. You don't want multiple control units competing with each other.

[wayfarer]

John West wrote:

I don't really understand the question. ... snip ...
Or are you talking about using an actual 6502 chip as the slice? That's ringing a bell - I feel someone's asked that before. I won't say it's impossible, but it certainly wouldn't be easy and the results are likely to be ugly. Bit-slices aren't independent and the 6502 doesn't expose the signals you'd need. Addition needs carry in and out of each slice, branches need to combine flags from all slices, and I can't imagine how addresses would work. And the 6502 is of course a complete CPU. You don't want multiple control units competing with each other.

This.

https://6502.co.uk/lesson/connecting-the-6502
viewtopic.php?f=4&t=5612&p=69249&hilit=bitslice#p69249

/SO, this is a Set Overflow, its not unused a lot, though it does still work. through, BE, RDY, Sync, ML, R/W and a few other pins, a second 6502 could be chained to a micro-sequencer, with a 16b cla module, and a few other bits, thats mostly a ROM, as long as the software is written/compiled, to do this. you might have to use an address pin for decoding, I dont think so though, whats there is 'almost' enough, if you have :

ProcB c= ProcA;

where A is the low byte and main cpu, and B is the extension cpu, then you are mostly copying data instructions on side by side locations, so an Address decoder, and microsequencer would have to be used to issue the op codes to each processor directly.
there are only a few operations where a 'carry' is required, and this can be accomplished using an interrupt between the cpus, or other uses of the R/W, and SO pins, through the decoder (which is a state machine, and must interpret these signals, use the SYNC and ML and BE lines to route the 6502 instructions and signals, cycle counts etc). A 6522 or similar chip may serve here as an interface here.

Building this sequencer is not exactly trivial, though seems as possible as using both phases of the clock for processing. It is likely that merely extending the busses in an HDL and implementing this with a few modifications is more practical and efficient on modern hardware, I think it can be done, the 6502 was not really design as a microslice processor per se, though it does have basic multiprocessing capabilities built in from the start.

...nearest I can spot, is using the irq-disable and /So pins. if we had the NC pin, I seem to recall one of the older chips having another pin not used lately...

[BigDumbDinosaur]

wayfarer wrote:

Could you bitslice  the 6502 so its 16d/16a, or 16d/32a ?

In theory, most anything thing is possible.  The more immediate question, I would think, is what do you hope to accomplish?

As John notes, bit-slicing was a stopgap measure devised to circumvent chip fabrication limitations during the early days when large-scale integration (LSI) was introduced to computer designs.  The primary driver of bit-slice technology was the desire for higher clock speeds and wider buses (both internal and external), which prior to the mid-1970s, was difficult to achieve in LSI.  Once chip manufacturers had mastered very-large-scale integrated (VLSI) circuits, increasing the clock rate and bus width became possible, and made the concept of a “one-piece” microprocessor economically practical.  Indeed, the refinement of VLSI was what led to the development of Motorola’s 6800, which, of course, spawned the 6502 family.

As VLSI became denser and denser, bit-slicing was no longer a necessity to get wide buses, and improvements to the CMOS fabrication process resulted in more-rapid switching speeds, negating the performance advantage of bit-slicing—and with much less power consumption.  Since the mid-1980s, bit-sliced MPUs have become as outdated in computers as vacuum tubes and drum storage.

In order for the components of a bit-slice MPU to work, some signals that are not externally exposed by most microprocessors would have to be made available.  Without those signals being present, gnarly timing issues would arise in synchronizing the two 65C02s.  Ironically, the 65C816 might be the better candidate for trying the bit-slice technique, since the VDA and VPA signals, combined with the current clock phase, MLB and VPB, can tell external hardware what is going on at any given instant.

That said, the question would remain as to what would be accomplished.  Other than as a learning and/or nostalgia exercise, I personally wouldn’t expect monkeying with bit-slice technology that involves the 65C02 to yield anything useful.

[wayfarer]

BigDumbDinosaur wrote:

wayfarer wrote:

Could you bitslice  the 6502 so its 16d/16a, or 16d/32a ?

In theory, most anything thing is possible.  The more immediate question, I would think, is what do you hope to accomplish?
.., ....  The primary driver of bit-slice technology was the desire for higher clock speeds and wider buses (both internal and external), which prior to the mid-1970s, was difficult to achieve in LSI.  ...
As VLSI became denser and denser, bit-slicing was no longer a necessity to get wide buses, and improvements to the CMOS fabrication process resulted in more-rapid switching speeds, negating the performance advantage of bit-slicing—and with much less power consumption.  Since the mid-1980s, bit-sliced MPUs have become as outdated in computers as vacuum tubes and drum storage.

In order for the components of a bit-slice MPU to work, some signals that are not externally exposed by most microprocessors would have to be made available.  ...
That said, the question would remain as to what would be accomplished.  ....

Wider busses and operations. the 6502 is an interesting architecture. it remains, after 50 years, a useful and well liked design,
I am no fan of the 65816 bus scheduling, which once in practice probably works just fine. Im planning to buy an extra 6502 soon, and after that Im grabbing an '816, just to use in "6502++ mode", using the simple 64k 16 bit addressing and using the newer features here and there. One of my projects is to get a 6502 on a 20b bus. having a 6502, or 65816 on a 32b buss, would be 'extra cool'. Im interested in new models of 6502 and 65816 designs that expose more functionality for the platform. It would be great if you could do this, and Im thinking that NC 'pin 35/39/33?' might have been a possibility at one point for 'microslicing' the 6502, though maybe the hi/lo clock cycling is a better way ?

in reality its probably easier to get a 6502 open core, and modify it to have these bus sizes and functionality, then implement that on fpga or asic/shuttle service. However, if a chip could be devised, and a compiler/assembler written for it that turned 2x 6502s into a 16x32b 6502, that was like 64 or 80 pins, and it just worked, would that be useful?

idk, just wondering if anyone had tried, and exactly what signal we need. Ill keep reading here and see if I can identify a path or method.

http://www.bitsavers.org/components/amd ... n_1980.pdf

https://en.wikipedia.org/wiki/Tile_processor (more like my 6404, or a bunch of 65'134/'122s on a buss)

a traditional dual 6502 processor is more like this, that uses 2-phase computing
https://en.wikipedia.org/wiki/Barrel_processor

[ttlworks]

wayfarer,
after reading your text I'm getting the impression that your intention is not to build a 6502 from Bitslice components,
but to use multiple 6502 chips like Bitslice components for building a bigger CPU.

//Maybe you should have phrased your first post in this thread a bit more clearly.

Please take a look at Jeff's KimKlone.

Jeff's idea was to give a 65C02 additional registers + instructions,
by building registers + microcode + logic _around_ a 65C02,
making creative use of the 65C02 NOP instructions.

This might be a nice starting point.

[wayfarer]

ttlworks wrote:

wayfarer,
after reading your text I'm getting the impression that your intention is not to build a 6502 from Bitslice components,
but to use multiple 6502 chips like Bitslice components for building a bigger CPU.
...snip...
This might be a nice starting point.

you have that ----- kinda----, Im trying to build a bit computer, from 2x, 6502s

https://laughtonelectronics.com/Arcana/ ... mmary.html

this, Im doing something similar kinda with isac