I will have to figure out how to prevent problems with MVN MVP
What sort of problems are you anticipating?
My simulator executes 65816 instructions in the shortest time of 250ns - longer about 500ns (does not emulate 65816 cycles exactly)
I want to get the fastest possible data transfer speed in DMA 1 byte per 1 6502 cycle, so if I send data to Apple2 RAM memory, then every few bytes I will have to perform one 6502 processor cycle to refresh its registers.
E.g. for 10us every 10 MVN or MVP instructions I will have to let the 6502 execute 1 cycle.
How do you plan to halt the 6502 while the simulated 65C816 is processing?
My Algorithm for DMA acces:
Only MVN and MVP codes can leave DMA LOW.
all DMA changes only in PHI_0 state
Except for first MVN or MVP and appleRAMI/O acces every MVP or MVN will be start in PHI_0 state.
Executing MVN or MVP :
1. check if AppleRAM or AppleI/O access needed
If not, execute MVN or MVP, go to 8
2. if DMA=LOW, go to 8
3. wait for PHI_1
3. wait for PHI_0
4. set DMA to LOW
5 set the DMAcounter to number of safe cycles.
6 wait PHI_1
7.DMAcounter-1
8.execute MVN or MVP
9.IF DMAcounter=0 or Last MVN or Last MVP then DMA-High
10 Next Opcode.
For interrupts, there are two possible solutions.
1. Treat multiple MVNs as one instruction.
2. Interrupt ends the DMA cycle
Last edited by gregorio on Wed Mar 12, 2025 11:51 am, edited 1 time in total.
How do you plan to halt the 6502 while the simulated 65C816 is processing?
Pulling the DMA pin on the Apple II peripheral connector halts the clock into the 6502. It also tristates the Address bus from the 6502s point of view - I'm not 100% sure about the data bus - my understanding is that the video clocks are still running so you can access RAM on the same half of the clock that the 6502 would normally access it, so single cycle writes (or reads) ought to be possible.
Just don't keep it halted for more time than you feel is prudent to preserve the internal state of the NMOS 6502...
In AppleII there is DMA access to RAM. It consists of stopping the 6502 clock. I have a question. For how long can you safely stop the 6502 clock in the LOW state in the MOS version?
In AppleII there is DMA access to RAM. It consists of stopping the 6502 clock. I have a question. For how long can you safely stop the 6502 clock in the LOW state in the MOS version?
That’s likely a pretty conservative value, but no point in trying to determine at what point the 6502’s registers will experience amnesia.
More concerning is the required timing for manipulating the DMA input. Its state has to be changed on the fall of the clock, but the above document doesn’t indicate how much timing leeway exists after Ø2 goes low.
Very interesting to see a definite number, from Apple no less, who would have had reputational and support cost reasons to be sure it's on the safe side in all circumstances.
No sir, the 65C816 in the IIGS is not static and as is the case with all 65Cxx MPUs, the clock can only be safely halted on the high phase. The IIGS went out of production about a year before the release of the static-core 816.
You're absolutely right and I'd forgotten that. I stand/sit corrected, sir.
