So the timing diagram on the datasheet shows that, with read handshaking, the CA2 signal on the 65c22 is active low (like CA1).
It seems to be outputting active HIGH signals. Is there a flag to control this? It doesn't matter necessarily, but I don't like un-explained behavior.
Also, the CA2 signals "data taken" basically simultaneously when the MCU signals "data ready" to the 65c22. Like, ~ 3 ns after. The timing diagram says it doesn't signal "data taken" until the input register is actually read, which at least on the diagram is a full clock cycle. I'm running at 1 MHz, so that would imply at least a full us before CA2 responds.
My setup "mostly" works, but is reliably unstable under certain circumstances. These two behaviors of the VIA seem like a clue. Thoughts?
Side note: "Reliably Unstable" would be a great name for an all female rock band. I jest of course...