The C128D revisited. A "what if" scenario

[kc5tja]

They used to publish the 68000 metric for the seive, but I see they no longer have this data. This seems disingenuous, but of course, it's possible that it was eating into their sales.

At any rate, it doesn't matter. A CPU shoot-out, a la the computer language shoot-out, seems like a better way of comparing CPUs anyway, assuming we normalize the results for clock speed.

[BigDumbDinosaur]

kc5tja wrote:

They used to publish the 68000 metric for the seive, but I see they no longer have this data. This seems disingenuous, but of course, it's possible that it was eating into their sales.

At any rate, it doesn't matter. A CPU shoot-out, a la the computer language shoot-out, seems like a better way of comparing CPUs anyway, assuming we normalize the results for clock speed.

And, as I said earlier, we're well off-topic. We shouldn't lose sight of the fact that this is a 65xx forum, not a 68K forum.

Every MPU design has its strengths and foibles. Key strengths of the 65816 are its versatility, high throughput as a function of clock speed, rapid interrupt response, straightforward bus system and ubiquity. Foibles? None that I would consider important, given the age of the architecture.

As for the 68K, good processor but actually kind of slow in some respects. I won't even get started on the 68K's lame interrupt performance. In some cases, the '816 can almost complete an interrupt service operation in the time required for the 68K to recognize that an interrupt has occurred.

[GARTHWILSON]

I don't think it's terribly off-topic, as the 68000 came up in the very first post regarding different directions the C128 could have gone, and the 68000 is being discussed WRT the 65816.

Anyway, I pulled out a pile of papers, and although I still didn't find the Sieve benchmark comparison I know I have somewhere (I think the '816 might have been just a tad slower than the 68K), one thing I found was the Dhrystone MIPS comparison. The 68000 is not on that table, but the 80386SL did 8 at 25MHz compared to the 65816's 4 at 8MHz. The 386SL was more than 10x the price. The 486SL did 18 Dhrystone MIPS at 25MHz, and was almost 40x the price.

Another table has speed estimates for various manufacturing scales for WDC parts. At .8µM, they're 20MHz and 14MHz for the '02 and '816 respectively. At .25µM (requiring going down to 3V), they become 205MHz (which has already been done) and 143MHz. At .18µM (requiring going down to 2.1V), they become 395MHz and 277MHz.

[Squeak]

As the thread starter, I don't think it's OT at all, and if you want to go off trail please by all means do, as long as it's a natural progression. There's nothing worse than someone who comes in and stops an interesting talk by pulling the OT card.
If you mean OT with regards to the forum, I don't think that's the case either. The overall topic is still the 6502 architecture and it's descendents. That's a very wide topic.

[BigEd]

GARTHWILSON wrote:

...didn't find the Sieve benchmark comparison I know I have somewhere (I think the '816 might have been just a tad slower than the 68K), one thing I found was the Dhrystone MIPS comparison. The 68000 is not on that table, but the 80386SL did 8 at 25MHz compared to the 65816's 4 at 8MHz. The 386SL was more than 10x the price. The 486SL did 18 Dhrystone MIPS at 25MHz, and was almost 40x the price.

Samuel posted some numbers in a previous discussion:

Code: Select all

Normalized performances:
  68000  8MHz = 0.49 seconds
  65816  8MHz = 0.73 seconds
   6502  8MHz = 1.53 seconds
   8086  8MHz = 1.90 seconds
   8088  8MHz = 2.50 seconds 

GARTHWILSON wrote:

...speed estimates ... WDC parts ... At .18µM (requiring going down to 2.1V), they become 395MHz and 277MHz.

I had no idea - that's really something. Our 5Volt world is not coming back.

[GARTHWILSON]

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I had no idea - that's really something. Our 5Volt world is not coming back.

Later I edited and added the words, "which has already been done" to the 205MHz number. One of WDC's licensees has been running a 6502 core in a custom IC at over 200MHz for quite a few years. I'm sure the memory would have to be onboard the same chip. And for newcomers, I'll repeat that WDC says the 6502 is being made in hundreds of millions of units per year today-- it's just that they're at the heart of custom ICs that people don't realize they own, in their cars, entertainment systems, etc..

As for the 5V world, it's not going away as fast as I had feared it would. More and more things are available in low voltages, but many will operate from 2V to 5V. This would not include the high-end processors, but all kinds of serial peripherals especially. And again, when it's SPI (or similar), there are very few lines and they're all monodirectional, meaning that voltage translation is pretty easy.

[Squeak]

kc5tja wrote:

There's only one way to solve this dilemma . . . MythBusters style! We should come up with some tasks for a 65816 and a 68000 to solve, and time each of them. Maybe we can pit an emulated IIgs against an emulated Atari ST, and see how they compete.

Rather baffling that any hobbyists haven't done this and published the results a long time ago.
But anyway, if the 65816 really is a tiny bit slower overall than the 68000 it would still have been a very good deal, especially considering that it could be used to replace IO controllers for disc and printers because of the great interrupt performance. And coupled with a DSP like co-processor it would have been killer.

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The Mac couldn't afford special blitters and dedicated sound hardware at the time, so they had to make do.

The Mac also used 4-cycle memory access, which like I said, dropped the 8MHz-clocked CPU to 4MHz equivalent bus throughput, and that's not counting the 4 cycles per memory access either. Even if they did have the hardware, they didn't have the cycles to use it all.

The Amiga didn't have this problem, so it had plenty of bandwidth for 64-color/4096-color (HAM) displays (though 16-color 640xH displays consumed 100% bus bandwidth). All of this is assuming OCS and ECS chipsets of course; AGA works very differently.

I don't see the problem with the Mac. It wasn't designed to work with co-processors, so they couldn't use the cycles for anything useful anyway.
The 68000 in the Mac wasn't slower than the one in the Amiga, it just had to do more work. It was frugal/spare/tight design, probably inspired by the Alto.

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You can do blitting in software very effectively. There were many add-on cards for PCs and Apple that allowed you to have similar or better performance in the same time frame and for approximately the same cost.

Of course, there are tricks you can play with software-only blitters: you can precompile blitter operations into machine code at run-time, and use that. I think Macintosh did that to push QuickDraw's performance as high as possible, sans dedicated hardware. Still, hardware blitting will be at least an order of magnitude faster.

Hardware blitting is of course just glorified DMA. There is nothing special or complicated about it.

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Well, Forth is nice because it's small, fast and has a healthy general approach to programming. . . . You can actually make great serious software in Forth,

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Oy -- my presentation at work is going to be on exactly this topic. I'm going up against a room full of Java coders. Wish me luck; this will be fun.

Well good luck, you are going to need it. I don't know where Java got all that wind in it's sails, when all the time (since 1980 in fact) there have been floating a balloon above, that held a far more complete idea of what OOP can be.

[GARTHWILSON]

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And coupled with a DSP like co-processor it would have been killer.

Now with memory so much cheaper, you can have megabytes of 16-bit look-up tables for super fast, accurate math. My plan for my next workbench computer (if I ever build it-- it has almost become a joke because I'm so slow) is to use the '816 and have 2MB of tables, so for example you can look up a sine or cosine or square root in about a microsecond, or, in only slightly more time, look up a 32-bit inverse which you can use for division. Division is always a big job, so if you can multiply with look-up tables, and have a quick way to get the inverse of a number, you can muliply by the inverse insead of dividing. The tables and explanations are available at the link above.

(Edited June 2012 after I got the math look-up tables material posted on my website)

[ElEctric_EyE]

You must @ least start. Will you wirewrap or dare to have a board made straightoff?

2Mx8, 10ns SRAM is cheap? ~$40, but 10nS. Biggest/fastest I could find. Running @3.3V it's sucking 275mA...

Or are you thinking DDR?+interface?

[kc5tja]

My Kestrel-2 was going to be wirewrapped originally, but if I go with an FPGA, I might consider dead-bug instead. See http://kd1jv.qrpradio.com/ap80/AP80.HTM for an example of this technique, used to build a radio.

BTW, Garth, don't feel bad about not getting your Workbench computer finished, or even started. You're not alone.

EDIT: http://elm-chan.org/docs/wire/wcd.jpeg provides a clearer conception of what I wanted to do. Using magnet wire to bond pins together, except that the chips are mounted upside down. OOoh,I just realized, this construction technique also lets me use BGA packages. I no longer have to fear them. Sweet!

[ElEctric_EyE]

kc5tja wrote:

My Kestrel-2 was going to be wirewrapped originally, but if I go with an FPGA, I might consider dead-bug instead.

kc5tja, I've read your posts from years ago, back from 2007 I think. Sounded like back then you were integrating FPGA's?

[kc5tja]

Yes. I was thinking of acquiring one of these boards https://xess.com/prods/prod035.php , and bolting a 65816 on some of its pins. The FPGA/CPLD combination would provide me with a 512-color VGA display (I'd prefer at least 32K colors, but I suppose I can take what I can get), SDRAM interface, and some other features in a package for about $200, which is what I'd expect to pay if I'd just purchased the parts myself individually and fabbed it onto a PCB.

Alternatively, I was thinking of using two of the aforementioned boards, with one of them the I/O functionality, and the other a stack-architecture CPU with MMU for running a multitasking Forth implementation with some degree of crash recovery.

It's been about three years since I last thought of doing such a thing, so I think we all know when this project will be completed.

[BigDumbDinosaur]

Squeak wrote:

As the thread starter, I don't think it's OT at all, and if you want to go off trail please by all means do, as long as it's a natural progression. There's nothing worse than someone who comes in and stops an interesting talk by pulling the OT card.
If you mean OT with regards to the forum, I don't think that's the case either. The overall topic is still the 6502 architecture and it's descendents. That's a very wide topic.

OT card? Now that's a new one. I'm not stopping anything. I was merely making an observation.

[BigDumbDinosaur]

GARTHWILSON wrote:

Quote:

And coupled with a DSP like co-processor it would have been killer.

Division is always a big job, so if you can multiply with look-up tables, and have a quick way to get the inverse of a number, you can muliply by the inverse insead of dividing. I already have the tables calculated and sitting in Intel .hex files, ready and waiting for me.

Of course, using 16 bit registers will speed up things a bit. Now that I have a working assembler on my POC, I'm going to revisit some of the math routines I've written and change them to use 16 bit operations. It'll be interesting to see how much of a performance improvement will be realized.

[Squeak]

BigDumbDinosaur wrote:

OT card? Now that's a new one. I'm not stopping anything. I was merely making an observation.

Nothing personal.