W65C134SXB - FIG Forth

[cheekyfox]

Hi All, I have a W65C134SXB board and connected this to an Atmel Max700S CPLD.

Progress so far:
1) Gated the reset line and Phi2 through the CPLD to produce a delayed rise on the BE line, Thus it now boots straight into the external rom reset vectors. ( Internal rom is disabled )
2) Got FIG Forth Release 1.1 running by:
a) hacking the provided monitor listing to get the UART running at 9600 Baud.
b) modifing the FIG listing to use the UART as the terminal.

Now looking closer at the startup, the manual states that after fclk is started, and I quote "The system software should wait (100 milliseconds or an appropriate amount of time ) " before switching from the slow clock (CLK) to the FCLK.

The question is what is the correct time for this? The monitor just loops for 256*5 cycles.

[BigDumbDinosaur]

cheekyfox wrote:

Hi All, I have a W65C134SXB board and connected this to an Atmel Max700S CPLD.

An Atmel Max700S?  That doesn’t sound like anything Atmel has ever prduced.

[cheekyfox]

Atmel Max 7128SLC84-15 to be precise!

[BigDumbDinosaur]

cheekyfox wrote:

Atmel Max 7128SLC84-15 to be precise!

The 7128SLC84-15 is an Altera part, not Atmel.  Atmel’s line of currently-produced CPLDs includes the ATF1502AS, ATF1504AS and ATF1508AS, in various speed grades.

[cheekyfox]

Maybe I am not that precise, you are indeed correct it is an Altera part. Using it as it has 5v input and output, so no need to level shift signals.

[BigEd]

Good to see you here again!

The delay is probably there to allow a PLL to start up and to stabilise. That's a difficult thing to characterise and it seems WDC haven't told us exactly what the limits are. I would think 100ms is always enough, but what they are trying to say with committing themselves is that you might be fine with less.

[drogon]

I bought one of these a good few years back thinking it might be a good platform but it gave me more headaches than solutions so abandoned it....

So well done for making something of this board - even if you did have to bolt on a CPLD to make it usable for you.

Eventually as part of another project - (My TinyBasic) I managed to get my own ROM running in it by letting their ROM boot the system, whereupon it checks for some magic in a part of the EEPROM and if present jumps to that - so my code disables their ROM with it's 'monitor' and replace it with mine using the facilities available on the board.

Which essentially means I let their ROM do the clock switchover thing rather than have to go through the cycle count shenanigans with BE to disable their wretched ROM.

I wrote enough IO for it to run my TinyBasic and use the EEPROM as storage but pretty much gave up on it after that - decided that it was a system going nowhere.

-Gordon

[cheekyfox]

Thank you BigEd, that seems to make sense that you have to wait for the PLL to stabilise before using the FCLK. Currently I just did the same as WDC did in their monitor, now I will instead of doing an emty loop I will use the time between starting the FCLK and using it to zero my page 1 memory.

And Drogon, I am only using a CPLD as it is easier that wiring up lots of logic chips. ( Also learning VHDL )

[drogon]

cheekyfox wrote:

And Drogon, I am only using a CPLD as it is easier that wiring up lots of logic chips. ( Also learning VHDL )

OK - Piqued my curiosity now - why use a CPLD (or wiring up lots of logic chips) when you didn't need to do any of that at all?

At least I didn't - just using the built-in mechanisms to get my own code going in the EEPROM and dispose of their built in ROM monitor after it's booted the system.

I acknowledge that "learning VHDL" is a good reason though...

-Gordon

[plasmo]

Instead of W65C134SXB, I used W65C134 chip and added CPLD and RAM. CPLD was there to help me experimenting with W65C134. Initially I had oscillator problem, but that turned out to be a design error. I’m able to run W65C134 to 14Mhz and eventually got rid of CPLD.

viewtopic.php?f=4&t=7913&
Bill

[BigDumbDinosaur]

cheekyfox wrote:

Maybe I am not that precise, you are indeed correct it is an Altera part. Using it as it has 5v input and output, so no need to level shift signals.

Atmel CPLDs offer the same capabilities and have the advantage of being currently-produced parts readily available from stock.  Something for you to consider for future development.

drogon wrote:

...decided that [the SXB] was a system going nowhere.

Gordon’s comment compels me to point out that the SXB unit is a reference design intended to get students interested in basic computer technology, as well as help sell the 65xx intellectual property to system-on-a-chip designers.  In my opinion, the SXB can’t really be thought of as a general-purpose computer.  Further to what Bill is suggesting, the 65C134 alone would make for a better GP computer, though not as good as what could be achieved with a discrete MPU connected to discrete I/O.

When the SXB boards came out 10-odd years ago, I was offered the 65C816 version gratis by WDC, as they were interested in adapting Fuzix to it and thought I might be willing to take on the project.  I was flattered, but also leery of what that might entail, as what I had seen of the 6502 version of Fuzix was not encouraging.  Being familiar with the complexities of implementing a preemptive, multitasking kernel on small hardware with no memory protection (I wrote such a kernel years ago to run on a 65C02-powered system), I did a deep-dive into the SXB unit’s design to gauge what I would be getting into.

I decided to decline WDC’s offer.  Simply put, I already had a 65C816 system (POC V1.1) that had more RAM, high-performance serial I/O (no 65C51), SCSI mass storage, and the capability of running at 12.5 MHz, which was 50 percent faster than the SXB unit.  I figured if I was going to invest time in porting Fuzix to the 65C816, I’d be better off doing it on my own hardware, since it already had the needed I/O capability (I subsequently dismissed the idea of porting Fuzix, mostly due to the lack of a decent 65C816 C compiler).

Bottom line is I tried to keep an open mind about the SXB unit, especially since its development was an effort by WDC to keep 6502 technology relevant into today’s world.  In the end, however, I came to the same conclusion as did Gordon.

[plasmo]

One useful application for W65C134 is a 6502-based flash programmer. One can learn about 6502 with a $15 W65C134 and a cheap 32K RAM and then add a socket for flash. No expensive flash programmer is required and one can use it to program new flash.
Bill