OT: MOS\CSG 5721R0 dissection, Amiga 2000 BUSTER

[barnacle]

As an aside - we've just done an exercise that compares using more expensive chips versus fewer components; we hadn't previously always compared board construction prices and it turns out it can be cheaper (er, more economical!) that way. Plus there's reduced failure rates for fewer components... I guess it's the same for the Amiga.

Neil

[LIV2]

Hi,

Thanks for posting this and the other Amiga related dissections! The Gary one was especially interesting to me as I have toyed with recreating Gary in a CPLD but have never gotten it to work perfectly
The behaviour of BGACK adding a waitstate was previously only vaguely documented in an old mailing list post - so it was great to see exactly what that did

Looking at Buster I think there might be a mistake with regards to the D2P in your schematic - it seems to show that D2P is switched between /OWN and /SLAVEn but that doesn't accurately describe the operation of the circuit

Furrtek also reverse engineered this from the same die shots I believe - their schematic is here and I've attached their D2P circuit to this post.

I reimplemented Buster in a CPLD a few years ago based off guess work, the equations from the A2000 Technical Reference and from observing the operation and below is the equation I came up with for this
From what I have read, the bug on the first revisions was that the buffers would be pointing in the wrong direction (should be pointing to the CPU side) when a Zorro DMA master was talking to a Zorro target, and this is show inside the "ifndef badbuster" section here in my verilog

Code: Select all

// Data buffer direction control
assign D2Pn = !(
  OWNn & READ & (!SLV[1]|!SLV[2]|!SLV[3]|!SLV[4]|!SLV[5])    | // CPU reading from Zorro card
  !OWNn & !READ & SLV[1] & SLV[2] & SLV[3] & SLV[4] & SLV[5] // Zorro master writing to mainboard
`ifndef badbuster
  | !OWNn & (!SLV[1] | !SLV[2] | !SLV[3] | !SLV[4] | !SLV[5])    // Zorro to Zorro 
`endif
);