Also conspicuous by its absence is any definition for RAM. Is there no RAM in this system? Also, it would be very helpful if you posted a full schematic, not bits and pieces.
RAM is the lower 32K of the 64K address space, and is controlled directly by the A15 line. I'll draw up a full schematic; lost the previous one.
You’ve got a timing skew problem with that arrangement. You should use the GAL to generate all chip selects so timing is consistent for all devices:
Code: Select all
FIELD addr = [A15..10];
RAM = addr['h'0xxx..7xxx];
I don't doubt that there's a skew there, and the plan has always been to replace this breadboard with a PCB with a 1508 to do all the address decoding.
Be that as it may however, I would think that if I am manually pulsing the clock and MANUALLY sending the write signal to the 16C550; presuming the skew isn't on the order of seconds, I doubt that's the issue here.
Again, everything works perfectly, just the UART throws a tantrum with whatever it's receiving from the 65816, and ONLY when I use the 65816. If I put the 6502 back in, it works flawlessly.
The VIA works fine, the RAM is working fine, the LCD works fine, the ROM is working fine; ONLY the 16C550C is having an issue. A 6551 does not have a problem, a SC26C92 has no issues.
I'm tempted to throw it behind the VIA and see what it does with that. =P
Schematic attached as promised without and with PLD version.
I omitted the bypass caps, but they are in fact there.
