ElEctric_EyE wrote:
In the past, when wiring data and address connections between CPU, SRAM, EPPROM and peripherals, I used to hop from CPU, to SRAM, to EPROM, etc., i.e. "tree" distribution. Now I wirewrap power, data, and address from CPU to SRAM, CPU to EEPROM, etc. Common sense tells you if you can keep all these IC's around the CPU, the distances would be shorter, but... Andre picked up on something here. I too am unfamiliar with electromagnetic workings inside the wire, skin effect, reflections, etc. I ask now because soon I will have to have PCBs made, very soon. I would like to get it right the first time. This could be a good thread to continue this topic?
When I was doing the POC layout I first looked at the idea of the MPU being in the middle and everything kind of fanning out from there. However, it soon became apparent that doing so would actually increase the aggregate length of the bus traces, the opposite of what was wanted.
After several iterations of the design, I came up with a layout in which the SRAM was immediately to the left of the MPU (which is in a PLC44 socket), the EPROM to the left of the SRAM, the watchdog timer to the left of the EPROM and the DUART to the left of the watchdog. The reasoning behind this is the SRAM is connected A0-A15, the EPROM to A0-A12, the watchdog to A0-A4 and the DUART to A0-A3. This arrangement makes more sense when you also consider that all of the decoding logic is attached to the higher addresses, thus adding some length to those lines. To minimize the trace lengths to the decoding logic, I placed those ICs immediately above the MPU.
In all likelihood, I was overcautious with my layout, as PC motherboards seem to be able to get away with some pretty long traces to the PCI sockets, all of which operate at 33 MHz (much higher for PCI-X and PCI-E). I also used a four-layer board, both to improve noise and layer crosstalk immunity, and to not have to route individual power and ground traces everywhere.
POC V1.0 Printed Circuit Board