W65C02S RDY / BE pins & first build advice

[BigDumbDinosaur]

Osric wrote:

In my case, I have created exactly the problem described - long curving wires for both the data bus and the address bus...I am expecting that when I test this setup at 1Mhz it will fail.

Maybe, maybe not.  A joke we have around here is you can get away with murder at 1 MHz.  That’s not entirely true, but applies to many cases.

The limit on how fast a given circuit will run, assuming the parts used have the necessary characteristics, is determined by timing constraints and signal quality seen at device inputs.  More specifically, long, curving wires typical of breadboards can introduce enough reactance into a circuit to where the sharp signal transition expected by a device’s input is not there, meaning the rise and fall time seen at the far end of the wire is outside of the specs for the device receiving the signal.  Adding insult to injury, wire inductance effectively adds propagation delay to the signal, which may sabotage timing.

So while breadboards are useful for prototyping circuits, they are not consistent in behavior as the clock rate is increased.  The point at which instability or failure will manifest itself will be strongly influenced by wire dress.  There are examples around here of breadboard circuits running at pretty high speeds.  What they all have in common is a wire dress that minimizes outright length, as well as plenty of bypass capacitors.

Quote:

I haven't yet had the time to do it but it seems like a simple test where I fill the RAM with a pattern and then check for its existence then fill with a different pattern ad infinitum will likely show a problem if I run the computer at a high enough clock.

Such a test will draw out any instability issues, but won’t necessarily prove that an implementation is stable under all reasonable conditions.  Most SRAM is much faster than ROM and I/O hardware.  So what seems to work okay with RAM won’t necessarily work with ROM and I/O.

Quote:

Once I do that and it fails, I'm left with the task of understanding why it fails. It seems that the reason why it fails (?) may be that the sharp rising edges on the long wires of the address and/or data bus may induce currents in the neighbouring wires and cause issues. Assuming that I want to make the breadboard build I have work at these speeds, I'll have to come up with some solution.

Mutual induction between wires is not usually the issue here.  Reaction in individual circuits is what results in slow edges.

Quote:

You've already told me that softening the edges isn't going to work but in fact will make the problem worse; I don't know why that is, but will have to learn.

It is the means by which you are planning to soften the edges that is the problem, not that the edges are softened.  Attempting to slow edges by adding R-C delay will cause a non-linear rise and fall, which may confuse CMOS inputs.

Quote:

Meanwhile, the twisted pair alternative presumably also won't work but the idea is not to twist each signal wire with an adjacent one, but to pair each address and data line with a ground line going to the same destination.

In high-speed parallel buses, such as SCSI, cable pinouts are arranged so each signal lead is separated from its neighbor by a ground lead.  Also, such buses are terminated at both ends to suppress signal reflections.  Such an arrangement is usually unnecessary on a PCB because runs are short enough to avoid transmission line effects at the speeds we usually operate our gadgets.  Now, if we were build boards using 1 GHz processors, it would be a very different story. 

Quote:

If all the signals and grounds are connected chip-to-chip in adjacent runs, I had thought that this would solve the problem. This too apparently will not work - I would have said it "resembles a ground plane" - and again is something I'll need to understand _why_ it won't work.

Understanding why it won’t work means studying the applicable theory.  There’s no getting around that.

[BigEd]

Just to note a couple of things... the most difficult thing to debug is a sporadic fail, an unreliable machine. That's the kind of thing which you risk building. If the thing you build is reliable, you can get on with software and with extending it. If it doesn't work, you can debug it. But if it very nearly works, that casts doubt on everything - that's the kind of problem to avoid. And this is where the quality of construction comes in. For sure there's such a thing as over-engineering, but do be aware there's a potential cost to just forging ahead.

The other thing to note is that almost everything happens as a result of falling edges of the clock. Almost every other signal can do anything in between times, so long as it settles in time to allow things to finish before the active clock edge. As a consequence, getting the grounds right, the power supply decoupled, and good clock connections will get you a lot of the way to a working system. (I say almost, because of course there's more to it than that. There always is.)

[J64C]

BigEd wrote:

(I say almost, because of course there's more to it than that. There always is.)

Absolutely! Just when you think you know it all and seem to have a good grasp on everything, something completely new crops up that throws a spanner in the works. Which reminds you that you are still scraping the surface.

[plasmo]

Osric,
Since you are in the exploratory mood, you might want to try a few things to check the margin of your design:
1. Lower the voltage gradually toward 3V; it should work down to 4.5V, possibly better due to reduced system noise. 3.5V operation is likely, unless you have voltage supervisor putting the board in reset.
2. Raised the voltage, but no more than 5.5V; everything is now sped up, so more system noise. This is where bypass caps are more important.
3. If you have a mean to apply controlled hot air over your board, try hot air up to 70 degree C. CMOS parts slow down when hot, but TTL sped up when hot, so it is a good test of design margin.
4. Back to room temperature and nominal 5V, try raising the clock. Chances are pretty good your design will work at 8MHz.
5. Remove bypass caps one by one. If your design is stable, you can do with fewer or no bypass caps.
Bill
PS, these are the things I used to do to qualify a product; heating/cooling new design in temperature chamber while raising/lower voltage; overclock by 33% and reduce bypass caps by 50%.

[GARTHWILSON]

Osric wrote:

Ground planes are literally in the fourth sentence of the primer's section on AC performance problems: "Solderless breadboards make for the longest connecting wires of any method (meaning most inductance), have extra capacitance between neighboring tie points, and there's no chance of getting anything even remotely resembling a ground plane."

When I read a sentence like that, I immediately wonder why twisted pair connections can't serve the same purpose as a ground plane for using solderless breadboards to prototype 6502 systems. It shines a light on my lack of knowledge of how this works.

I did say "remotely resembling a ground plane," but I can see the possible cause of confusion.  I'll try to find a way to edit it to clarify without making it any longer than necessary.  A tight grid of ground connections on a board without a plane will, to a limited extent, resemble a ground plane.  The slower the edge rates (again, it's not the MHz), and the shorter the connections, the less risk there is of trouble.  And although most breadboard designs work, we do get some percentage (10%? 15%?) that don't, and newbies can't figure out why, when schematically all the connections are correct.  It leads to frustration, which we of course want to avoid.  OTOH, if we come across as insisting that you have to understand it super well, I know that could be frustrating too.  I hope to just make people aware, so that without understanding the details, they practice good construction habits so the problems never arise.

Keep telling us what you took it to mean though, so I can keep improving it.  A couple of entities have asked permission to make a curriculum book out of the 6502 Primer, and I have asked them to please just refer students to the website because I am always improving it, which of course I can't do to a book that's already printed.

Regarding twisted pairs:  Even a straight piece of wire has inductance.  Wire-wrap wire has about 20nH per inch; and increasing the wire size has very little reducing effect, meaning you'd have to increase the wire size dramatically to get even a small reduction in inductance.  When you send a pulse down the wire, the sudden change of current changes the magnetic field around the wire, and that magnetic wave travels outward.  It also opposes the change in current, pushing back, in the opposite direction, kind of like a flywheel resists being accelerated or decelerated; but if there is a return wire right next to it, the changing magnetic field will also push electrons in that wire, trying to make them go the opposite direction, to minimize the change in the net flow.  While the wire inductance is generally undesirable, this mutual inductance is a good thing.  The Cray-1 supercomputer had miles of wire-wrap wire and clocked at 80MHz; but it was all twisted pairs, and the special insulation on the wire had a very low dielectric constant to improve propagation velocity, so electrically the wires did not look so long.  (That's about the sum total of my knowledge about the Cray.)  Having all the pairs on our boards twisted would generally be great for performance, but highly impractical to build with.  One end of a pair would have to go to a signal pin and a ground pin (which unfortunately can be kind of far apart), and the same at the other end.  The area between the wires has to get charged up, requiring and storing energy, so it's good to minimize that area.  Having them close together, like they'll be if they're twisted, does that.  (Then we could get into characteristic impedance and terminations; but you can ignore that if they're short enough relative to the edge rate, again meaning that short connections and slow edge rates make it much more friendly.)

In the mid 1980's I worked in applications engineering at a place that made VHF and UHF power transistors mostly for military radars and communications.  I had to get really cozy with the Smith chart and transmission lines.  We did actually use transmission lines sometimes to change balanced signals to unbalanced or vice-versa, or even swap hot & ground.  [Edit:  I posted about that, with diagrams, at viewtopic.php?p=52943#p52943 .]  We mostly dealt in the frequency domain there, whereas in digital, we mostly deal in the time domain, so it's a little different; and after that job, I started getting into a little digital, and then into switching regulators which don't switch that fast in terms of MHz, but their astronomical rates of change in current (δi/δt's) can make them a challenge, and even an extra eighth of an inch of connection length can have a harmful effect on the regulator's behavior.  So interestingly, although I have not worked with the GHz+ stuff in nearly 40 years, I have continued improving my understanding of this stuff.  I don't have access to the expensive test equipment anymore, so I just exercise that nebulous term "good engineering practice" to avoid problems.

plasmo wrote:

1. Lower the voltage gradually toward 3V

That brings up an interesting thing I hadn't thought of before.  WDC's parts are specified down to less than 2V (1.8V or even 1.2V IIRC, depending on the part), and of course they (along with edge rates) get slower at the lower voltages, as would be the case with 74HCxx logic too; so running at lower voltage would make it more friendly to non-ideal constructions.

[Osric]

GARTHWILSON wrote:

And although most breadboard designs work, we do get some percentage (10%? 15%?) that don't, and newbies can't figure out why, when schematically all the connections are correct.  It leads to frustration, which we of course want to avoid.  OTOH, if we come across as insisting that you have to understand it super well, I know that could be frustrating too.  I hope to just make people aware, so that without understanding the details, they practice good construction habits so the problems never arise.

I don't have time for a proper response just now but really wanted to respond on this one point: I really appreciate the time and effort people are putting into their posts on my topic and am not a person who is easily frustrated, whether by forum posts or by debugging problems of my own creation.

The desire to "understand things super well" is my internal desire, not something I think the forum or primer is pushing on me! My need to dig into issues deeply/understand them to the bottom is tightly intertwined with my desire to follow an incremental approach, without which I would not be able to make any progress. I seem to be rather resistant to just "following good practice" without understanding it.

[Osric]

BigDumbDinosaur wrote:

Osric wrote:

In my case, I have created exactly the problem described - long curving wires for both the data bus and the address bus...I am expecting that when I test this setup at 1Mhz it will fail.

Maybe, maybe not.  A joke we have around here is you can get away with murder at 1 MHz.  That’s not entirely true, but applies to many cases.

I guess part of the problem is I'm willing to "get away with murder" in order to limit the amount of learning I need to do to make progress; and what everyone's afraid of is that I'll get into such a snarl as a result that I'll give up when things suddenly stop working reliably. I'm less worried about that than about not being able to make progress at all.

In any event, I finally had time to play with this a little bit. I adapted the code you provided in another thread to make a super-basic zero page RAM test as follows:

Code: Select all

  .org $FF00

reset:
  lda #0
  tax
  sec        ; set carry to rotate it through

bittest:
  sta $00,x  ; set up to test address x by shifting
  ldy #9     ; the carry bit 9 times -> C 0000 0000,
             ; -> 0 0000 000C -> ... -> C 0000 0000
bitloop:
  rol $00,x
  dey
  bne bitloop

  bcc bitfail_stuck_off ; Carry bit didn't make it back!

  lda $00,x   ; no bits should still be on in address x
  bne bitfail_stuck_on

  inx
  bne bittest

pass:
  nop
  nop
  nop
  jmp pass
;
bitfail_stuck_on:
  lda $00,x
  lda $00,x
  jmp bitfail_stuck_on

bitfail_stuck_off:
  lda $00,x
  jmp bitfail_stuck_off

  .org $fffc
  .word reset
  .word $0000

This runs fine at 1 Mhz and 2 Mhz on my breadboard. At 4Mhz it fails most mysteriously, with the PC winding up in the middle of nowhere. However, as I don't want to run the computer that fast yet I can safely ignore that; it's not really unexpected, as I didn't consider speeds higher than 1 Mhz at all. Unfortunately at 1Mhz micropython is no longer fast enough to keep up for the debug monitor, and for that matter I haven't confirmed that USB is fast enough to make that work well either, so I will probably need to get distracted writing the debug monitor in C or even in PIO with DMA. A project for another day...

BigDumbDinosaur wrote:

The limit on how fast a given circuit will run, assuming the parts used have the necessary characteristics, is determined by timing constraints and signal quality seen at device inputs.  More specifically, long, curving wires typical of breadboards can introduce enough reactance into a circuit to where the sharp signal transition expected by a device’s input is not there, meaning the rise and fall time seen at the far end of the wire is outside of the specs for the device receiving the signal.

I am still in the process of learning enough to understand this sentence. Reactance (and therefore inductance) are not terms I feel I understand fully, so I have a ways to go here. My limited understanding so far is that reactance means that while current is changing the long wires act as resistors and slow down the current getting to steady state, with a voltage drop of L (di/dt) ... and presumably this is why fast edges are a problem, as the faster the edge the larger di/dt is and the bigger effect we see from the relatively small L values even in short wires (looks like it's about 150 nH for 100mm of wire). Exactly why this resistance wrecks the signal at the other side isn't clear to me. In addition I've read that CMOS inputs have very high impedance so essentially no current flows - but if no current flows, then I really don't understand how reactance works. So a lot more research is required to learn these things...

[Osric]

plasmo wrote:

1. Lower the voltage gradually toward 3V; it should work down to 4.5V, possibly better due to reduced system noise. 3.5V operation is likely, unless you have voltage supervisor putting the board in reset.
...
4. Back to room temperature and nominal 5V, try raising the clock. Chances are pretty good your design will work at 8MHz.

At least one of my parts has 4.5V as the bottom of its voltage range - if memory serves, it is the AT28C256 EEPROM. Would you expect it to work so far out of spec?

My breadboard already fails at 4Mhz, so I guess the 8Mhz test will require work first. All of these other things I should have a chance to try in September, when I have access to my electronics work area again ... right now I am working on a coffee table, which is distinctly sub-optimal

[Osric]

BigEd wrote:

Just to note a couple of things... the most difficult thing to debug is a sporadic fail, an unreliable machine. That's the kind of thing which you risk building. If the thing you build is reliable, you can get on with software and with extending it. If it doesn't work, you can debug it. But if it very nearly works, that casts doubt on everything - that's the kind of problem to avoid. And this is where the quality of construction comes in. For sure there's such a thing as over-engineering, but do be aware there's a potential cost to just forging ahead.

Yes, I can appreciate how winding up with a flaky system could be very difficult indeed to deal with. I'll have to cross that bridge when I come to it; for the moment I'll hold on to the hope that I can take small enough steps that I can understand the failures when they crop up, but recognize that if the failure is the accumulation of a half a dozen small unrelated sins, it may be next to impossible to isolate even if I took baby steps to get there...

[GARTHWILSON]

In the restrooms where I went to high school, the sink faucets had a spring return, to save water.  There was no damping on it, so if you let go of the handle quickly, the faucet would close instantly, and the inertia of the water coming in the pipe, as it tried to keep going, presented a super high pressure.  You may be familiar with the term "water hammer."  That's what this was.  If it's bad enough, the water hammer can break pipes or valves, as the pressure peak flies up for an instant.  I don't know what plumbing structure lay hidden in the walls and floor; but when someone would do this, we could hear a back and forth banging, as that peak was reflected from one end to the other and back, in pipes.

A similar thing happens with the current in the wire.  The wire has inductance, which acts like inertia for the current.  It tries to maintain whatever level the current was.  The CMOS ICs' inputs, although not accepting DC current, have a tiny bit of capacitance, like a very small amount of springiness, like a hard superball which bounces really well, so when a pulse comes down the wire, it tends to bounce back toward the originator.  The originator has a very low impedance; but there's also inductance in its ground connections which cause a brief change in the reference voltage, fouling things up, if switches there turn off or turn on fast enough, especially if it's doing lots of these at once, like a data bus.  (If there are actual transmission lines, as opposed to free wires, they can be terminated, which mostly gets rid of this problem; but it requires making the terminating impedance to approximately match the characteristic impedance of the transmission line, otherwise it won't really help.)

When you put the whole mess together, you can imagine how the echoes and reverberation can create quite a grand mess, and in all this ringing, the positive and negative peaks may be extreme enough to change the logic state. If one or more lines go to any kind of edge-triggered input, you may get multiple clocking edges when the logic has not had time to process previous ones, which is why the clock distribution is the most important part of the circuit to keep clean. For data inputs, even if the ringing is bad, the circuit may still work fine if you slow the MHz down enough to give time for this ringing to die out before the next valid clock edge; but the clock signal still needs to be pretty clean.

See also my post at viewtopic.php?p=789#p789, with the analogy of what happens when there's too much inductance in the ground connections between ICs, and viewtopic.php?p=55450#p55450 describing why decoupling capacitors at each IC, although good, can only go so far in fixing this problem.

[Osric]

GARTHWILSON wrote:

A similar thing happens with the current in the wire.  The wire has inductance, which acts like inertia for the current.  It tries to maintain whatever level the current was.  The CMOS ICs' inputs, although not accepting DC current, have a tiny bit of capacitance, like a very small amount of springiness, like a hard superball which bounces really well, so when a pulse comes down the wire, it tends to bounce back toward the originator.

I am going to take quite a bit of time to understand what you’ve written here properly, including reading the referenced threads which I haven’t done yet. But I wanted to ask a question first because I have just formed a mental model of what “inductance” is, and I want to see if that mental model is correct (or at least not misleading).

Like a lot of folks, as a teenager I thought of electricity like “water in a pipe”. But I think this analogy is fundamentally unhelpful because when you apply pressure (“voltage”) at one end of the pipe it is easiest to think of it as instantaneously appearing at the other end of the pipe (assuming the pipe is full of water). Perhaps if I had thought of it as “empty pipes” that would have been a better mental model.

In any event, I am now trying to think of things differently and would love it if we could confirm that my new mental model is either correct or at least not misleading. My new mental model is that the electric field represents the force applied to charges in space, but it takes time to set up the electric field surrounding any conductor, and the time required depends on the “inductance”. That is, when we first send a signal into a wire (pressure / voltage), the signal will take time to set up the electric and magnetic fields that will cause the electrons to drift through the circuit. This setup time exists whether or not the circuit is open or closed; again, our teenage selves are used to thinking of a circuit as “doing nothing” when it is open, but in fact when we apply a signal at one end of a wire what actually happens is that the electromagnetic field gets set up, charging the wire to the potential that we’ve applied if it is open, or causing current to flow if the circuit is closed. That’s why in the famous veritasium video on the thought experiment of the switch 1m away from the light we can detect that current starts to flow through the light long before the current starts to flow through the circuit; the electromagnetic field reaches across the 1m gap to cause a small amount of current to flow through the bulb even if the circuit is open.

So, even if CMOS inputs have infinite impedance, when we send 5V down the line to ship a bit to the IC, we have to wait for the setup time of the electromagnetic field - that is, we have to take into account the inductance of the wire. The longer the wire, the more the inductance, and the longer the setup time for the electromagnetic field.

I realize that is not the end of the story, but is that correct so far, or am I confused?

TIA,
Osric

[Osric]

GARTHWILSON wrote:

A similar thing happens with the current in the wire.  The wire has inductance, which acts like inertia for the current.  It tries to maintain whatever level the current was.  The CMOS ICs' inputs, although not accepting DC current, have a tiny bit of capacitance, like a very small amount of springiness, like a hard superball which bounces really well, so when a pulse comes down the wire, it tends to bounce back toward the originator.  The originator has a very low impedance; but there's also inductance in its ground connections which cause a brief change in the reference voltage, fouling things up, if switches there turn off or turn on fast enough, especially if it's doing lots of these at once, like a data bus.  (If there are actual transmission lines, as opposed to free wires, they can be terminated, which mostly gets rid of this problem; but it requires making the terminating impedance to approximately match the characteristic impedance of the transmission line, otherwise it won't really help.)

OK I spent some time trying to understand this and made some progress, but still have some misconceptions that mean I don’t think I am getting it right. Here’s how I currently understand your paragraph:

1- As a signal comes towards the CMOS IC’s inputs, it encounters some capacitance on the input. Capacitance acts as a short circuit until it is charged, so initially some current will flow into the CMOS IC input and down to “ground” via the CMOS’s ground pin.
2- Once the capacitance is used up (which should happen awfully quickly), the inductance on the signal line wants to keep current flowing in that direction. The reason for this is that when the CMOS input pin is up to 5V and the capacitance is used up, current will actually stop flowing, and when current stops flowing the magnetic field around the inductor (that is the signal wire) will collapse, and when the magnetic field collapses, that will try to keep current flowing but there’s nowhere for it to go. It reflects back towards the source IC (and we can’t put a backwards diode across the inductor because it is the entire signal wire; though perhaps if we carried the signal with 10 or 20 wires we could lower the inductance?)
3- This is where I get confused; we start to talk about impedance in the ground connections of the originator. I do not understand this part. My best guess based on what I’ve tried to understand is to imagine the originator is driving a bus, like a data bus, and sending 0xFF down the bus - now it’s switching 8 outputs at once. On either end (rising edge or trailing edge) this is going to cause some ground bounce, but it seems like the ground bounce is really only going to cause us a problem on trailing edges because there’s less margin in our logic signals on the low side than the high side: and when the signals go from 0xFF to 0x00, the inductance between the transmitting chip’s ground reference and the system ground cause issues.

Perhaps an experiment could help me measure this. If I put an oscillator into a buffer or inverter chip, driving all the inputs simultaneously, and connect the buffer to ground via a long wire - say perhaps a 30cm coil - I ought to be able to see the ground bounce by probing the ground pin to system ground as well as disturbances on the outputs by probing an output pin? My oscilloscope has only 2 channels and is only 100Mhz, and I’m not that familiar with using it, but it seems like an experiment like that might help me understand, if it’ll work.

Also more clarity on what’s happening at this stage/where my misconceptions are would be helpful.

[BigEd]

Although it's possible to understand things all the way down at the physics level, and the physics level is what underpins any folk model, I think it's advantageous to have that folk model in hand. With a folk model, you can predict what the circuit will do. With the physics model, you have another level of foundation underneath as to why that is so.

My own model was for a long time a model without inductance. That did very well for the sorts of things I needed my model to do. If you must account for inductance, then I would recommend thinking of it as momentum for the current.

So
- level 0, put things together and see if it works, then change things until it does, or until you run out of patience
- level 1, have some rules of thumb as to what is good practice
- level 2, have some folk physics to explain what happens in a good circuit or a bad one
- level 3, apply electrostatics and electromagnetics to the circuit as a physical system
- level 4, add in relativity and quantum mechanics because you demand to understand everything all the way down

I would advise against hopping about between those levels.

It's quite possible to be a successful hobbyist with level 1, and it is less frustrating than operating at level 0.

[Paganini]

Osric wrote:

Like a lot of folks, as a teenager I thought of electricity like “water in a pipe”. But I think this analogy is fundamentally unhelpful because when you apply pressure (“voltage”) at one end of the pipe it is easiest to think of it as instantaneously appearing at the other end of the pipe (assuming the pipe is full of water). Perhaps if I had thought of it as “empty pipes” that would have been a better mental model.

That's also how I learned the basics in 4H club. I also think it's a bad analogy. Water runs downhill. The explanations and illustrative diagrams always confused me because I couldn't figure out how gravity fit into the picture. Nowadays I think of it as *air pressure.* This is not necessarily better, I guess, but at least it makes sense to me!

One thing that might help, maybe, is to notice that there is not really any such thing as a "signal" moving in the wires. The idea of "signal" is an abstraction that lets us think about logic instead of electrons. Similarly, "voltage" is not a thing that moves around. Voltage is a measurement taken by us, the observers, that describes the relationship between two points in a circuit. What we are measuring, specifically, is the number of free electrons (or "electron holes" that free electrons could move into). In the classical model, because Ben Franklin was a bit of a goober, the point that has more "electron holes" is positively charged, while the point that has more free electrons is negatively charged. If you connect the two points with a conductor, the free electrons will move from the negative point to fill in the holes at the positive point. Classical current is the movement of the "electron holes" in a conductor, but what is really happening is that electrons are zipping around in the *opposite direction.*

Ideally, all points in a circuit that are electrically common have the same voltage (0V) when compared to each other. If we add some "electron holes" (say by attaching the positive terminal of a battery), we can "see" them at all the points electrically common with the battery. (I mean, if points A, B, and C are electrically common and we attach a 9V battery to point A, when we measure voltage between A and B or A and C we don't see 9V; we still see 0V.) This is (at least for CMOS logic) what enables the digital signal abstraction.

Suppose we want to send a signal from (say) a clock generator to (say) a 6502 processor. We make the 6502's clock input pin electrically common with the clock generator's output pin (we connect them with a wire). To send the signal, the clock generator changes the voltage on its output pin. That changes the voltage at the 6502's clock input pin. All the 6502 has to do is "notice" that the voltage has changed.

Ideally, all points in a circuit that are electrically common have the same voltage (0V) when compared to each other. In reality, though, electrons move very quickly, but *not instantaneously.* So, it takes the tiniest bit of time for the battery to "suck" the electrons out of the circuit and charge up points B and C. How long this is depends on how big the wire is, what it's made of, and what else is going on around it. But more importantly, to change the voltage at the 6502's clock input pin some electrons must move. Those electrons come from somewhere! Where? The answer is ground. The ground side of a circuit is like a free electron reservoir. If some electrons go out from the clock input of the 6502 into the clock output of the oscillator, then the same amount of electrons must also go into the 6502 through its ground pin. This means that, temporarily, the 6502's local ground pin is slightly more positive than the rest of the ground side of the circuit. Meanwhile, the oscillator has a few extra free electrons that it just received from the 6502. It has to send those electrons back to the 6502 so that the free electron reservoir can settle down. If you don't suck, you can't blow. This is the signal return path. Unfortunately (in some ways) for us, electrons like to take the path of least resistance. If the loop back between the ground pins of the oscillator and 6502 is long or windy those electrons will try to find some other way to go, which can include through other ICs that might happen to be in the way. Havoc may ensue.

Moreover, as the oscillator switches voltage at its output pin and the 6502 follows almost (but not quite) instantaneously at its input pin, tiny amounts of current will be constantly flowing back and forth between those two pins, and also between the two ground pins of those ICs. Even though our (logic) signal is (abstractly) traveling in one direction (from oscillator to 6502), we are actually dealing with alternating current! We potentially have to think about capacitance, inductance, impedance and all kinds of complicated math. Because of electromagnetic fields we might experience intermittent glitches on a signal caused by complex relationships between switching patterns of *other signals.* This is why Ed keeps talking about rules of thumb. To debug these sorts of problems you need (often very expensive) equipment, and a real command of electronics math. This is something that most hobbyists (including me!) would rather avoid.

Finally, I guess it's worth pointing out that even the classical model is not "what's really going on." As Ed says, you can go all the way down to quantum mechanics, where electrons are not "things" that "move" but are more like ripples in fields. Every model is a description in some sort of language, more or less precise, of what we observe. There is no "what's really going on" that we can access independently from our perceptions. At some point you have to stop looking for the next turtle down and start building computers.

[Osric]

BigEd wrote:

- level 0, put things together and see if it works, then change things until it does, or until you run out of patience
- level 1, have some rules of thumb as to what is good practice
- level 2, have some folk physics to explain what happens in a good circuit or a bad one
- level 3, apply electrostatics and electromagnetics to the circuit as a physical system
- level 4, add in relativity and quantum mechanics because you demand to understand everything all the way down

I guess I plan to do exactly what you recommend against and I should spend a bit of time understanding your objection/what the disadvantages are.

Before I explain my proposed plan, it might be worth thinking about “why am I doing this” or “what is my goal, anyway”. I think I already said my goal is to build a 6502 machine of approximately the capability of the Apple II clone I owned as a teenager, for fun. To be a little more precise about it, I embarked on this exercise because a friend was visiting and said “why don’t we build some retro computers for fun” and so we started doing that; in the bigger picture, I already have more retirement projects than years of life expectancy so every project is competing with many others (I limit myself to 50 activities/year, in an attempt to ensure that I don’t just hop from thing to thing constantly … arguably 50 is too many). In this case, I am finding it lots of fun to build a system from the ground up, understanding the actual wiring, the memory map, building a trivial little development and debugging environment, etc. It’s fun to see it work, but it is also fun to find out where my prior knowledge is flawed or lacking and understand things properly.

And that’s where my approach seems to butt heads with your levels and your advice to not hop between levels. Because basically I am operating somewhere between level 0 and 1, with a little bit of experience from having built circuits over the last 40 years or so of varying complexity (TTL door locks with my kids to teach them about logic gates and electromagnets, RC airplane speed controllers, strobe lights for tuning my floppy drive for the aforementioned Apple II since it wouldn’t stay spinning at the same speed for more than a few weeks at a time, and so on). I haven’t built very many circuits (more than 40, fewer than 200) and have almost never built a production circuit (something that I expect to run unattended - to really work, in other words).

So my plan was to work at this level relying on my past experience, but each time I hit a roadblock dig down to the bottom or close enough to it in order to truly understand why my previous knowledge was insufficient. So in the case of inductance for example, thinking of it as “inertia” will probably model a lot of situations and let me make reasonable decisions, but it isn’t inertia and part of the fun for me would be understanding what it actually is. Calculus seems a lot easier to me in my old age than it did as a student in university, so dealing with the math is not really a hurdle anymore. Finding coherent explanations that actually seek to explain things at a low enough level has actually proven to be the main challenge thus far.

Since part of my goal is to learn things, and the excuse for learning things is hitting walls in the project (but the cost of learning anything is very high because I want to dig down fairly deep, at least to level 3 and perhaps to level 4), I was thinking I could go ahead and build tiny-stepwise, learning as I encounter obstacles. However as you explicitly recommend against this, I’m interested in why you see it as a problem?

If a the end of the day I’m going to read a bunch of hand-wavy application notes and decide “I’ll do it this way because it’s good practice and it’ll work” I imagine that I would reach a working computer faster than if I follow the approach I am following … but what will I do with that computer? Stick it on a shelf, because fundamentally coding in assembly for a 6502 is not, for me, of particularly high interest except as part of the larger project of understanding electricity properly.

As a post script, I should maybe mention that the other related project I am pursuing at the same time is to try to understand radio properly. The SDRs you can buy these days for next to nothing are quite amazing. Many of the same things I don’t understand about electronics will apply to radio transmissions too, so the overlap in these two projects is potentially useful.