How well does SRAM cope with floating address pins when it's enabled (/CE, CE2) but neither outputting (/OE) nor storing (/WE)?

I am designing a read/write-round-robin-algorithm for SRAM in a VGA circuit and was thinking about how strict I need to be about always having some kind of data on the address bus.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I forgot to mention, I am not talking about the 6502 bus, as it's a completely separate design that I want to interface using address and data-latches, in a first incarnation connected to the 6522 in some way, then if successful, later on integrated in the SBC (with the latches connected using memory mapped I/O).

What I have in mind is to have something like a 74AHC138 cycle through the lowest 3 bits of a column value, and one of the '138 outputs will trigger a write to RAM from the above mentioned latches, and 2-4 of the other will do various reads from memory for a simple state machine to form the next 8 pixels to be displayed. Kind of. Then there might be a few outputs from the '138 left unconnected where nothing is driving the address bus (I don't think I need to do 7 memory accesses per 8 pixels and I am thinking of leaving some "padding" around the write to avoid bus contention).

Sounds like, while not ideal, it will be kind of OK to leave the address bus floating for a few ~80ns periods (a 12.5 MHz pixel clock).

(FWIW the RAM in question is an Alliance Memory AS7C164A-15PCN and I am using all CMOS ICs, some HC, some AHC)

Actually when I think about it, it might be better to let the "write-latch" drive the address bus for half of those 8 steps (say using bit 2 of the x-coordinate as latch output enable instead of an output from the '138) and then put the /WE trigger from the '138 somewhere in the middle of those 4 steps to be sure memory corruption is not an issue. That also leaves less steps to fill and reduces floating bus time that could possibly cause some ruckus. Sorry for the sudden rubberducking