Edit: Problem was in slow edges - using Schmitt triggered 74HC14 in place of 74HC04 fixed it. Also there was two problems in schema, which I fixed along the way.

Short: it works with jumper cable but fails with jumper wire and I am confused

Long:
I am trying to read PS/2 keyboard and I would like to read each byte in paralel similar to Ben Eater.
I wired something on breadboard, and it did not worked. I realized, that for my PS/2 keyboard are pullups necessary. I put the connector and pullups (3.3 kOhm) on universal board for mechanical stability and got some results.
Then I rewired all the Rat Nest Cables with neatly organized U-wires and it stopped to work. After some testing and debugging (with the Rat Nest style again) I found, that all works when there is one specific cable and changing it to wire makes it to fail. And it can be repeated.

The idea is simple, put data to shift registers. As the clocks start by falling edge, invert it to start with rising edge, like 595 likes. Make another clock with little delay (2xNOT) to fetch register for displaying. See, if it works, then try more following steps.
Here is the schema



Picture in color, the culprit is on the top left - the red cable vs. the white wire


Here it is in BW, it works with the CABLE (top left), Stop bit is clear.


And when the cable is removed and the same holes are used for a wire, it fails and Stop bit is lit. (usually the second 8-leds are all on or all off, acording to the 8.Led on the left - which is bit 6)


And here is the same picture, with wiring enhanced (some wire are not (good)visible in the photo)


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I would like to know, why such small difference (connect two points with something else) make such big difference in result (it works or no). I tried more different cables and made more wires too, but always cable works and wire does not.
I think, that there is some noise involved, but I do not understand, how it could affect the SECOND shift register. And how I can get rid of it, so my experiments on breadboard will be reliable again (and so it works, when transferred to PCB later).
There may also be some other problems involved, which I just do not see at all, or I did not understand something right, but I am now totally confused. Can somebody tell me, what is wrong?
Thank you in advance

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Power issues can cause this type of behavior. Add some bypass capacitors (eg 0.1uf) on the power rails next to the power pin of each chip and a larger capacitor (eg 100uf) near where the power connects.

Also, if you happen to be using ‘AHC’ logic, I’ve found these harder to use on breadboards successfully as the transition from high to low on outputs is faster than e.g. the ‘HC’ logic and can cause reliability problems.

-Phil

Fascinating! I really like your diagrams. Do you have a scope? It would be interesting to see what that clock signal looks like at the counter input pins with the wire vs. the jumper.

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My suspicion is that the cable has a pin on the end which is slightly thicker than the wire. One or both of the ends is perhaps failing to make a good contact to the metal clip under the plastic.

Does the signal buzz through (on an unpowered circuit) between the IC pins?

Neil (who hates proto boards for this very reason )

I added two 10 uF condensators to power lines and three 66nF condensators over chips (best I have at hands at this point), also I grounded the chain of unused NOT gates to minimise noise, but no visible difference.

All I have are Gabotronics XScopes XProtolab - slightly better than nothing.
There is some software for it, which enable mouse setting parameters, but the screen is pixel to pixel perfect copy of the miniLCD, just drawn in smaller pixels, so no added information and I did not snap it.

The voltage shown is either zero or 5V, Channel 1 is Clock, left wire (black), top line, Channel 2 is Data, right wire (red/grey), bottom line, Trigger is on Data fall edge, moved to left part of screen.

Here goes unfiltered Clock and Data, as they goes out of the PCB part of schema


Here are Data and Clock after one NOT gate and "problematic wire"


and here is Clock after one NOT gate and "problematic wire" compared to Clock after three NOT gates (delayed) - the delay is not visible, the shape is the same


And zoomed - the quality is bad, as I could not use flash to see the dispayed data and had to use more hands, than I actually have, to take the picture, but the result is readable and correct, just little blured pixels

For my eyes this seems to be good and clear shapes, one pixel noise, edges not totally perfect, but really good - but I may miss something.

This is scan code for key "Y" on autorepeat, as it shows single clock data and also missing Stop bit

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Well, it's not that big difference if you remember that even when the circuit seems to be "working" it is still suffering from a lot of noise. Changing the wire didn't really change much; it just happened to tip the balance slightly.

It's hard to know what to suggest, but here's an idea or two which may help... or not! (This is in the spirit of, "what can I try that's easy." rather than "what would be the ideal solution.")

I'd begin by changing where power and ground enter the project, attaching the + lead and 0 lead from the power supply so it goes directly to the '595s and to the LED assemblies as shown below. That's because these are the points which most directly attach to the heaviest and noisiest load (which is the LEDs, switched by the 595s).
For a bit more effort, you could try this (below). Note the extra connections on the left, and I have added a "CAP." It could be a 10uF, a 66nF, or -- better yet -- one of each! (in parallel)

-- Jeff

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This remark puzzles me somewhat. Perhaps it's just your explanation which is confusing me, and there is no need for concern. But the register clock is RCLK, and the circuit shows it gets its signal BEFORE the delay, not after. Is this what you intended? (BTW I'm not saying this is relevant to the symptom you mentioned. But it might be.)

-- Jeff

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TL;DR;
Probabelly it was spikes/noise on slow edges. Resistor fixed it, maybe Schmitt-trigger 74HC14 will help, I will try ity soon.
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Yes, you are right, I made a mistake and confused meaning of RCLK and RSCLK (which shifts and which latches). And it shows the lights all shifted (off one error).

(BTW: What is the accurate differentiation between these two in English? )

I tried to improve power filtration - made pair of caps for each IC (120nF), also I made the power for PS/2 to go right along the Clock and Data lines and put grounded wire accross the LEDs input lines, but it did not help


Here are the caps, also see, that the wire is the same width as the cable (right bottom for comparation).


The power is transferred to the breadboard from this cheap laboratory source - so it is 5V and 0.1-0.2A depending on number of LED shining (and it limits the current, so it is sefa from shorts). I made my own connectiion to the board 2x3 pins + LED (left bottom-center) in my photos it is usually on the top, near the ICs (thick cable for 240V - flexible and low resistance)

The wires (stripped from one long ethernet cable) should not be problem too, as PC/s is 10-16.7 kHz and I buid this 3MHz with them and no problems with bad connections (some problems with power distribution, so I will make external power bus to each breadbord line later)


I tried many improvements, but with better connections and filtrations it all went only worse, so I came to idea "what if the wire is not too bad, but too good?" which make sense for me (the "wire" connections are usually more reliable, then the "cable" one) and switch the "problematic wire" for random resistor (3k3 was the nearest to grab] - and it worked! I then shorted the resistor and it came bad again. I halved the resistor by placing other one in paralel, still worked. So I tried more resistors, worked with anything I had at hand - so I ended for now with the lowest value (and biggest footprint, but it fits nice there) - 10 Ohm - and it works regardless filtration or not


So the schema is now this way


I suspect, that as the fall and rise edges of PS/2 are slow, that there are some "spikes"/noise when the NOT gates convert it to digital 0/1. My scope is not able to see that, it would need another magnitude of quality/price tool for it.
(Ben Eater hit similar problem after adding capacitor-resistor-diode combo to detect the clock active block - the end rised too slow and made lot of really short spikes - he send it to Schmitt-trigger NOT gates - 74xx14 in place of 74xx04)
So I will wait, until my batch of 74HC14 arrives (I ordered them some time before for something else) and I will try to replace it too, to see, if it helps.
Probably the same is also on the latch channel, but excessive latching on the same value does not have visible result (instead of excessive shifting in more values).

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TL;DR;
Probabelly it was spikes/noise on slow edges. Resistor fixed it, maybe Schmitt-trigger 74HC14 will help, I will try ity soon.

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Yes, I totally agree. But here the breadboard is for prototyping, before I will move it on PCB.
So far I found out, that PS/2 need pullups, that I made mistake in my design and that there is real problem with noise (and I will see, if it can be fixed by the Shmitt-triggers). And there is also something I would like to test about SW part. (So far I saved 3 iteration of PCB, which are both money and time like month or two)
The real target is Comp24 build on 10cm x 10 cm stackable PCBs.
Similary the 3MHz, which I mentioned is also part of this work - it proved, that I can have two clocks in system, one for CPU, other for ACIA, it proved, that I can manipulate also VIA and PIA and there are some tests I want to make and it allowed me to test all the ICs I have bought, if they even works. I want also test something about time interrupts and about traffic controll (CTS/RTS).
Again the real target is Comp24.
In my experience, if I can make something work on breadboards, it will work also on PCB, and better with higher frequencies. So I usually find common pitfalls on breadboard, then move all to PCBs for more permanent use.


Yes, I bought "fistfull" of both ceramic and electrolytes for this, now I have to wait until they arrive. And there is no advantage, to have them just sit in drawer, when I am testing something on the bench
(I found I have really bad technology debt now, so a lot of my time is spend with catching up on the basics, like power source, soldering tools, LED indicators, resistors, wires, just nearly anything, what you would just reach to the drawer without thinking. I reach to drawer and found I am missing some basic prequisities, but they also have prequisities and so on and so on... This also contains SW and knowledge how to use it, like KiCad, Gimp, Krita, openScad, ... and datasheets and ... well, nearly anything ...).

I mean the difference, where the longer one have pins on ends and is of some excessive leght so it can be sticked all around, roud and waving in the air (and usually have multithread core) and is HW equivalent of KiCad "Rat Nest Wires" going in the air and to be materialized
and the shorter one is cut to particular length in 1/10 of inch, straight and right angled and is meant for more permanent use and is equivalent to KiCad copper traces, already having position, direction and place

AsSo the question is, how would you formulate something like "I replaced all the jumpers with jumpers to have it more clean, mechanically resistant and compact". So far I used "cables" for the former (longer) and "wires" for the later (shorter), but I do not know, what english speaker will call it, if he would like to explain it. In czech I would use "kablíky" and "drátky" which is basically "multicore"/"singlecore" but overlaps and many people use it interchangably.



On the start of this discussion I found out, that this circuit works with cable, but does not work with the wire (more short and tight jumper) and called the place "problematic wire".
Later I found, that this problem is repeatable even when all kinds of power improvement was taken. (Like bypass capacitor, routing, ...)
Later I found, that the problem is, that the wire is just "too good connection" and that it can be simulated by placing resistor there (3k3, 1k6, 220, ... just any I had in reach), so I ended with the lowest I have here now - big white ceramic "5W 10 Ohm" one. On the scheme it is the one just under the title "This works" with sad emoticon near it, as I am not happy with this solution.
Also this one (random and improvised resistor) fits to the place naturally and is visible reminder, that there is some really problematic, which have to be improved later. (And that it is this one exact place/connection)

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I'd probably refer to a flexible wire with a some kind of plug on the end as a jumper and the single core shaped version as a wire, possibly qualifying as 'cut and shaped to length (single core) wire', if it needed clarifying. But English has the same confusion over wires and cables and jumpers and whatever - except that I would consider a cable as something with a plug/socket connector on the end and a wire as something off a spool/reel, cut as required.

(I grew up in broadcasting, where a jumper is both a single-core twisted pair(!) to be soldered or crimped into a jumper frame block, and a short length of flex cable with audio jacks on each end to be used on a patch panel... oh, and short video cables which are single solid core but two outer braided cores...)

That said, your English is a damn sight better than my Czech will ever be; I'm having enough trouble trying to learn German.

Neil

Thank you barnacle, I think that "flexible wire" versus "solid wire" would work really good for me in this context

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It's a pity there's ambiguity. The pre-formed and pre-cut jumpers are nice to use when they are the right length for the job. The ones with connectors on the ends also add two connections, internally, which could add resistance.

If added resistance is helping, that might indicate one or more things:
- fast edges causing ground bounce, which means you need more local decoupling or better ground distribution
- early signals causing violation of hold times or clock skew, which means you need to check your logic design for race conditions and your clock distribution
- fast edges or glitches causing malfunction, for example SRAM chips can be quite fussy about input signals

Today arrived 74HC14 Schmitt- trigered NOT chips, so I changed it with the 74HC04 NOT and it worked even with the "problematic wire" and without any capacitors and power enhancements at all - so the problem was in the slow edges of my PS/2 vs. fast gates with large "forbiden/grey areas".

Also I found and fixed error in the schema (RCLK vs. RSCLK) and improved it (not little delay, but other phase instead - way more reliable and sufficient for the usage), so I can do next step and try decode it in CPU and if it will work (it should), then next step will be to finally do stable PCB

As for pre-cut wires - they fit the right lenght as I pre-cut them on the breadboard, where they are planned to be

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