Our forum user kc5tja has published this article on how to use SPI as a kind of GPIB replacement:
https://falvotech.com/tmp-blog/20240207.html

I found it actually really nice, but noticed he hasn't posted it here, so I'll do it.

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

I'll also re-post my comments I made on mastodon here as documentation:

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very well thought out!
I suggest an error bit in the length field so that the device can signal unrecoverable problems during read and the need to end the tx and read the error chan for details.
And maybe a note that deselecting the device from the controller cuts any transactions short, and the device should just assume data transferred so far, and on next listen/talk continue with the next bytes
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I believe the error bit would handle the case where e.g. a drive reacts with read timeout.
Sorry if I have missed how you handle this situation
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I know there are several devices that use a status return like you propose to throttle transfers. How do you imagine this being implemented?
If a device is really slow, a processor would probably not be able to do that reliability. Do you imagine some hardware support?
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Another thing. Do you want to mandate a specific SPI mode? Working with different modes can be a pain depending on your hardware support. I'd suggest mode 3, which is the one the VIA shift register and the 74LS164 do out-of-the-box.
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André

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Note that the 65SIB has an /IRQ line, so that a protocol could specify using that to alert the host that there is some device that has a critical error.

Also note that some SPI devices report error conditions by the value returns on a host byte out cycle, such as giving a function token or a segment address, where a 0 back on all bits is all clear, and a 1 back on any bit is an error condition. Typically that is an error state, so if the error happens before sending bit 5, the MISO byte is %00000111, but in any event, if the SPI_TRX return accepts the MOSI byte in A and returns the MISO byte in A, and loading the MISO byte is the last action before RTS, then the Z flag returning from those actions will indicate whether there has been an error return, and if the Z flag is considered too easily over-written, returning an error state in the C flag would only add 4-5 clocks to SPI_TRX.