there are other DIP SRAM chips that are a lot faster, the W241024AK for example is "only" 128kB but also has an access time of 10-15ns.
but you'd need 4 of those, which will overall be more expensive than a single 512kB chip
They have an 8KB High RAM window in the 16bit memory map, so an 8bit latch for the high address lines of the HighRAM gives 2MB, and the Dev Board has sockets for four 512KB SRAM ... so using 128KB would be 4-16 of them.
though ironically, if they didn't stick with their "as much DIP as possible" thing they could've saved some cost and made it run at +16MHz by using the IS61C5128AL, which is a 10ns 512kB SRAM chip in a TSOP-44 package that only costs half as much as the AS6C4008 (current mouser prices).
If they didn't stick with the "as much DIP as possible", it seems like they could replace most of the glue logic in the system with a CPLD. And of course if I filter the 512KBx8 parallel 5v search at Mouser by surface mount, I see a 10ns surface mount 512KB for under $4.50 with over 500 in stock, and a 25ns surface mount with over 5,000 in stock.
The cost reduced X16 console seems like it will be all-surface mount, with a soft core YM2151 on an FPGA replacing the old-stock / pulled YM2151 chips, so it seems likely to have a 25ns or 10ns SRAM soldered onto the board, and any YM2151 speed constraint seems like it would be able to be eased as well, but since the Console is going to aim for compatibility with the first generation Dev Board, the design isn't likely to be reworked into, eg, 12.5MH RAM full speed zone and a 6.25MHz ROM / YM2151 speed zone.
but i guess the overall idea of the X16 is modularitiy and tinkerability (if that is a word) and not absolute performance. then again because they did use DIP, someone could in theory make an adapter for the faster chips but it would also require some extra work on the rest of the board to make running at a higher clock possible.
Well, it's Dave's dream computer, My preference would have been 65816 from the outset and 12.5MHz to have the system clock in sync with the internal 25MHz pixel clock of the VGA video chip, with clock stretching to 6.25MHz for the ROM part of the memory map, but different people have different dreams. I do know that the clock speed selection circuit is based on a counter, so the choices are powers of two, but I don't know whether accommodating the YM2151 and its 4MHz clock made the next option after 1/2/4/8 into 2/4/8/16, where 16MHz just isn't practicable with a 65xx bus with 55ns SRAM.
However, since he also runs the smaller 8bit Keys channel, it wouldn't be
surprising if he was willing to compromise top speed to accommodate the YM2151 -- an 8channel 4-op, 4 waveform, ADSR envelope FM chip supports a lot of Genesis type chiptunes that would be hard to convert to play on Vera's 16 channel PSG without hardware ADSR envelope. Some people might not realize that an FM chip with only sine waveform needs to use two operators to emulate triangle, sawtooth or square waves, so for a number of patches, 4-waveform, 4-op FM is akin to 1 waveform FM with 5 or 6 ops.
