I’ve got my Ben Eater 6502 and Worlds Worst Video card kits and I wanted to add double buffered video to my system as easily as I could.
I read everything I can around here and at Wilsonminesco.com and I did a lot of Altavista queries, checked out Usenet, did some Gopher library browsing, logged into my local BBS, the usual…..
Anyway, I figured it out.
But I sure spent a lot of time on the memory setup.
One thing is that wanted to add to my system while keeping the memory mapping of the existing hardware the same while adding this Double Buffered Video.
The Ram is right there. 16 juicy kilobytes sitting unused.
I just needed to access it!
The 1 chip NAND decoding used in the system is so clever because it does so much with just the one chip. 16K RAM, 32k ROM, and a VIA and ACIA (or more!) all decoded and ready to go with the 1 chip.
Doing anything to improve on it adds to the build pin count quite a bit and leaves unused gates.
But…
To add a double buffer to my VGA setup I needed to use some of the unused upper 16k of the 32k SRAM.
The problem is the NAND decoding setup writes to RAM when you write to your IO chips in the IO address range. No problem if you never read or show that RAM!
Now that I do, another NAND gate, and a NOR gate fixes it.
With that in place a AND,XOR,and OR gate each get me a setup where I can enable or disable Double Buffered video and change the displayed buffer with a couple of VIA pins. The ‘off screen’ video ram is always presented to the system as being 8kb at location $2000 and the circuit shows the ‘on screen’ memory without any intervention.
I’m pretty happy I figured this one out. Just a few cents of 74 series chips and a huge enhancement in the video capabilities!
- Double Buffered VGA and Mem Map Fix
There are two ways I could do this;
In the same address space as the ROM so that writes to $8000+ are blind writes to the character screen, and reads are still reads from ROM.
That won't work as is because the ROM will be outputting when that range is accessed for writes.
Another NAND gate on the Read/Write line used as an inverter and used as the ROM Output Enable fixes that issue.
Likewise, if I wanted to put 4k of Dual Port RAM at address $7000 the VIA will get selected.
That takes yet another NAND as a inverter and a OR to fix.
I really see why folks eventually play with a PLD for address decoding, but I still like how easy it is to do quite a lot with just a few 74 series chips.
The added 4 74 series chips, and a few gates already present get the mods on the attached image done.
I’m pretty happy with the results!
- Lets Scroll software sprites using a Double Buffer!
)