But another secondary concern (and going off topic a bit) is running the VIA at high speeds. Not to give away all my plans, but I'm not seeing a great deal of viability with the 65816 + VIA. Correct me if I'm wrong, but the addresses and CS lines must be set by the time PHI2 rises. On the 6502, that's no problem because it drives all of the addresses during PHI2-low also. But on the 65816, it drives the lower addresses, but those higher addresses are not yet available until PHI2 rises.
No; the only delay is what's in the '573 transparent latch. The fact that it's transparent while phase 2 is low means the high address bits do come through before phase 2 rises; then they are latched at that point to remain there while the data bus switches to data. So it's no problem.
But another secondary concern (and going off topic a bit) is running the VIA at high speeds. Not to give away all my plans, but I'm not seeing a great deal of viability with the 65816 + VIA. Correct me if I'm wrong, but the addresses and CS lines must be set by the time PHI2 rises. On the 6502, that's no problem because it drives all of the addresses during PHI2-low also. But on the 65816, it drives the lower addresses, but those higher addresses are not yet available until PHI2 rises.
No sir.
All 65C816 address information is available during Ø2 low—A16-A23 appears on D0-D7, and it all appears at the same time.¹ The WDC rendition of the VIA should have no trouble keeping up with the 65C816.
Where you are likely to run into trouble is in your glue logic. I recommend you not use 74HC and instead use 74AHC, if a 5 volt system. Otherwise, cumulative prop delay is going to get in the way. This is especially critical with the bank bits latch, which needs to be very fast to avoid timing contretemps.
—————————————————————————————— ¹“At the same time” means within 1-2 nanoseconds of VDA and/or VPA going high.
Last edited by BigDumbDinosaur on Sat Oct 28, 2023 9:02 pm, edited 1 time in total.
But another secondary concern (and going off topic a bit) is running the VIA at high speeds. Not to give away all my plans, but I'm not seeing a great deal of viability with the 65816 + VIA. Correct me if I'm wrong, but the addresses and CS lines must be set by the time PHI2 rises. On the 6502, that's no problem because it drives all of the addresses during PHI2-low also. But on the 65816, it drives the lower addresses, but those higher addresses are not yet available until PHI2 rises.
No; the only delay is what's in the '573 transparent latch. The fact that it's transparent while phase 2 is low means the high address bits do come through before phase 2 rises; then they are latched at that point to remain there while the data bus switches to data. So it's no problem.
Ah ha! And hence the use of the '573 vs. '574! Got it Ok, thanks for that Garth, I finally understand why they went that way now.
All 65C816 address information is available during Ø2 low—A16-A23 appears on D0-D7, and it all appears at the same time.¹ The WDC rendition of the VIA should have no trouble keeping up with the 65C816.
Where you are likely to run into trouble is in your glue logic. I recommend you not use 74HC and instead use 74AHC, if a 5 volt system. Otherwise, cumulative prop delay is going to get in the way. This is especially critical with the bank bits latch, which needs to be very fast to avoid timing contretemps.
—————————————————————————————— ¹“At the same time” means within 1-2 nanoseconds of VDA and/or VPA going high.
Right. I got it now, I see what you mean. I was expecting it to *drive* the upper addresses, but I wasn't thinking they were *available* because they were behind the latch. But as Garth said, it's transparent, and as long as you leave /OE low it's good to go!
Right. I got it now, I see what you mean. I was expecting it to *drive* the upper addresses, but I wasn't thinking they were *available* because they were behind the latch. But as Garth said, it's transparent, and as long as you leave /OE low it's good to go!
Yep. You drive the latch’s /LE input with the Ø1 clock. When Ø1 is high (Ø2 low), the latch is transparent and the Qs follow the Ds. Within a few nanoseconds after Ø1 goes low, the latch closes and maintains the state of the Qs.
The time it takes for the the latch to close on the fall of Ø1 is a potential timing “gotcha.” If the latch is too slow, it will not close before the 65C816 stops emitting the bank bits on D0-D7 and data appears. Such an event will likely result in the A16-A23 address component becoming corrupted. I don’t think I need to describe what sort of mess that will make.
At 4.5V, the 'HC573 requires an 8ns hold time at room temperature and a 10ns hold time over "industrial" temperature ranges, which are both met by the '816 running at 5V - but only just. You would need to take a lot of care over the skew between the complementary clocks being provided to the CPU and the latch, especially since the latch enable also needs to be qualified by any RDY signal you might be using, which will tend to make it lag the Phi2 clock.
The 'AHC573 requires only a 1.5ns hold time, which is much easier to meet, and AHC gates to generate the appropriate latch-enable signal will help stay within that.
... But another secondary concern (and going off topic a bit) is running the VIA at high speeds. Not to give away all my plans, but I'm not seeing a great deal of viability with the 65816 + VIA. Correct me if I'm wrong, but the addresses and CS lines must be set by the time PHI2 rises. On the 6502, that's no problem because it drives all of the addresses during PHI2-low also. But on the 65816, it drives the lower addresses, but those higher addresses are not yet available until PHI2 rises. ...
That's not technically true ... per the '816 datasheet, at +5v the higher addresses are available on the data bus a maximum of 33ns into the first phase of the clock cycle (and as with all of the 65c816 datasheet timings, that's probably conservative from having a slower process when the timing was first certified), and the bank address is still valid on the rising edge of PHI2.
As Garth, Chromatrix & BDD note. All of my ramblings on gate delays at faster speed are wiped out by BDD's advice to use AHC process parts, so deleted.
Ok, thanks for that Garth, I finally understand why they went that way now.