I have a front panel program for Z80 version of the trainer. Its description is on this thread and posted on Apr 20, 2022. I believe I've implemented all the functions described in that post. The CPLD design file is attached. On a later front panel board for RC2014, I've added a 'x' command that allows any address to be entered while in the data entry mode, but I'm not sure the trainer has the extra resource for that command because it does extra Z80 functions such as address decode. I don't think the lack of 'x' command to access any arbitrary address is too big of an issue because most manually entered program starts from 0x0 and you can only manually entered limited size program even with PS2 keyboard method of data entry. 50-100 opcodes seem to be the limit of my patience, so using carriage return and backspace to move forward/backward of the code space is not too limiting, IMO.

For the front panel to work, the flash memory is removed, so only Z80 and RAM are populated on the trainer.

Regarding the 4th processor, I think 68008 may be interesting. The routing around the group of processors may be exciting, so possibly 4-layer PC board is needed. Signal integrity is not really an issue so I'll just let the autorouter does its magic.

Looking at your schematic, I believe it can accommodate both W65C02 and W65C816.

Bill

Edit, I mentioned in the Apr 20, 2022 post that I'll describe the front panel functions in detail later. I thought about it, but it was too complex to explain, so I never did explain, at least not in a generic, systematic manner. The design is in schematic so I'm happy to explaina specific circuitry if you want.

By the way, the last parts for the board arrived, so here are some photos.

If you look carrefully, there are some minor errors (mostly at silkscreen), that (all of them) have been corrected at the Z80_SBC.rar gerber files I posted.
1) At silkscreen layer the text about RAM and ROM says "40pin", but it's actually "32pin", and Mbit changed to KByte values.
2) The "HALT" signal of the Z80 processor is an output (and not an input as I thought), so I can't use T7 (CPLD signal) to control the Z80 running state. As a result, the "jumper sign" below JP4 (this is a connector, not a jumper anymore) is removed in silkscrren layer. Of course, someone can still use a jumper at T7 - HALT position to pass tha Z80's HALT signal to the CPLD at T7 signal pin.
3) At silkscreen layer the surrounding of the crystal oscillator socket (Y1) shows more clearly the position for a 4-pin square oscillator (The small version of these). (and something about the position of the pins in the middle of the socket !)
4) At Top and Botton signal layers the routing for the main power switch (S1) has been corrected so that the switch's rocker arm position matches the silkscreen "ON" and "OFF" indications on the pcb.
All have been corrected.

Good news, the 4 CPUs version of this board is also ready. Now it supports Z80, 65C02, 6809 and 65C816 !
Gerber files are here !
The schematic changes are only at "MCU" section, and this schematic shows below.

Looking good!

Maybe it is not necessary to have two separate sockets for 65C02 and 65C816. Since the pins that are different are going into CPLD, you can just change the functions of pins in CPLD. So it is same socket but different CPLD. That was my solution for CRC65 rev2.
Bill

I'm sure you will have a great deal of exploration fun and many possibilities with your board. I have had some fun with Plasmo's (Bill) versions and I appreciate that he has helped me to expand the uses with his other boards like the VGA6448 and the proto3 for adding a CF card on the RC6502 connector. I enclose a couple of pictures as an example.

CPLD Trainer supports several different processors plus the logic is programmable so you'll quickly find several boards are needed to support the various options. I've built 6 boards and still need more to support other project ideas. So order 10 boards and that still may not be enough.