The J64C

[J64C]

plasmo wrote:

40Mhz is realistic. I have a hand wired design that does 40Mhz with elevated supply voltage of 5.4V. I have a revised pc board coming in next week that I hope to run 40Mhz at nominal 5V.

50Mhz is incredible!
Bill

Sorry, to get your hopes up. I just ammended my last post there. I was running through a clock divider still. So 25 MHz it is right now.

Will still be pursuing how fast I can push this. You still hold the crown as fastest, by a long margin.

Hopefully, if nothing else. You now know that the figures I report are in complete honesty.

[plasmo]

Oh, OK. I’m excited that more people are looking into overclocking 6502 with different set of hardware. I think using 65C22 as the I/O device has great overclocking potential.
Bill

[J64C]

Will certainly keep you posted. It got to 25 MHz effortlessly. So I am hoping I can squeeze a lot more out of it.

[J64C]

Decided to start getting back in to this today.

I have disconnected the GameDuino (as the display solution) and have decided to have a go at making my own using a CPLD, which won't get me far to start with due to limited capacity, I know. But I have managed to create a low res graphics area on screen.

It's currently sharing RAM from location $0000 onwards, with the CPU and I am running a program to act like a big 5x5 black and white cursor, so I can see that the CPU is stable. It's cool as you can see the zero page calls at 0 to 4 running realtime and can also see the stack. I'll look at moving the location later on.

There is a bit of tearing going on, which I will look at resolving today, as a result of line noise and probably also the lack of capacitors on the CPLD test board. Otherwise the image is extremely clean. As always pics don't do it justice.

The graphics board uses the low side of the clock, putting the CPU in to the high impedance state, which causes a big performance penalty, due to the recovery time of the CPU on the high phase of the clock. Without going for the datasheet, (from memory) it takes up to 25nS for the CPU to come good again, when BE goes high. And yes, in practice, that does affect things quite a bit.

I could go down the path of dual port RAM one day. But for now, I'm just working with what I have.

[J64C]

The clock to the CPLD was a little verbose, so I inserted a 100 Ohm resistor at the CPLD side which has settled it down a bit. Also eliminating all of the tearing at the edges of the screen.

Before:

After:

Turns out you couldn't visually see the stack in the last pic either, due to the noise, causing a misread of the CPLD or something. It can be seen with the additional coloured pixels, which are flashing away real-time as the CPU does its thing.

[J64C]

A quick drop in to say I've been making some seriously ridiculous progress on the J64C lately.

I even have it running Commodore 64 ROM's to get it to run BASIC etc. C64 compatibility isn't the end goal at all, but gives a hell of a test environment to play with.

Even expanded the standard capability of the C64 graphics to have 24 sprites and a palette of 512 colours (RGB range and 24 sprites seen in the above pic).

[BigDumbDinosaur]

J64C wrote:

Even expanded the standard capability of the C64 graphics to have 24 sprites and a palette of 512 colours (RGB range and 24 sprites seen in the above pic).

Are you still generating with a CPLD?

[J64C]

Nope. Upgraded to the bigger brother, the FPGA.

The CPLD wouldn't go anywhere near close to this, unfortunately. Unless I stacked up a whole heap of them.

[Agumander]

Quote:

I could go down the path of dual port RAM one day. But for now, I'm just working with what I have.

They're getting more expensive and with longer backorder times. Going with dual ported RAMs is my one real regret about my GameTank.

I *definitely* don't have any ulterior motives to discourage their use such as reducing competition in sourcing the chips

[J64C]

Haha!

Don’t worry, I’ve gone down the path of using dual port RAM without using dual port RAM.

[J64C]

Had some thoughts that popped in my head to greatly increase the speed of my project, on a couple of fronts. Without spilling the beans before trying out this ‘theory’, I need to brush off this project and doing some serious testing.

It may amount to nothing, but if my theory is right, could end up with some ridiculous speeds. As a refresher, I have cracked the 40 MHz mark, albeit crashy, if you look at it the wrong way at that speed.

My goal is to do Plasmo proud. Ha!

[plasmo]

Waiting with bated breath.

[BigDumbDinosaur]

J64C wrote:

My goal is to do Plasmo proud. Ha!

Don’t take too long...Bill is starting to turn a little blue around the edges. 

[J64C]

BigDumbDinosaur wrote:

J64C wrote:

My goal is to do Plasmo proud. Ha!

Don’t tale too long...Bill is starting to turn a little blue around the edges. 

Haha! I think we all are. I'm certainly feeling it and I'm the "spring chicken" around these parts at the meagre age of 50.

I am actually planning on doing some designing today on KiCad so I can get a little prototype board done. My strip board project is getting a little unwieldly and my OCD levels are blocking me from being creative (even though I have enough of it together to test this stuff). Haha!

Maybe some staring at KiCad will spark the brain in to the correct mode along the way. Will keep you posted.

[J64C]

Placed an order for the boards. Made this one a 32K one to keep complexity down and also making it able to reuse my existing components. If all (or even some) of the concepts I want experiment with work out well, I'll make a bigger better version later on.