VIA control line question

[allisonlastname]

I'm working on getting SPI working and I decided that it would be easiest to use the VIA's shift register for data out and a separate 74HC595 for data in, owing to the fact that the VIA's SR skips the first input bit unless you put a flip-flip in the way. However, I'm having trouble generating the RCLK input for the '595. If I use the same signal (CB1) for SRCLK and RCLK, the value on the pins lags one shift behind the actual internal value, so that's not useful. My (extremely janky) solution is to use CB2 as RCLK, on the grounds that it doesn't matter whether the incoming byte is clocked onto the pins until the transfer is finished, and it doesn't matter what CB2 does unless the clock is pulsed. However, directly setting the value of CB2 didn't work on my test program, but it did on a smaller test that only manipulated CB2. Can you only manipulate CB2 directly when the shift register is disabled?

Rough schematic:

output.pdf

(107.83 KiB) Downloaded 116 times

[Dr Jefyll]

Here are some thoughts, though perhaps no complete "solution" -- sorry!

allisonlastname wrote:

Can you only manipulate CB2 directly when the shift register is disabled?

That sounds right (although I haven't checked).

Quote:

[...] owing to the fact that the VIA's SR skips the first input bit unless you put a flip-flip in the way.

Adgain, I haven't checked. But I would've though the extra flipflop you mention is required only when the VIA inputs a clock signal that's generated externally (rather than outputting a clock that's generated internally). Suggest you search the forum (or Garth's site) for doc on VIA bugs.

Finally, your RCLK issue will disappear if you switch out the '595 and instead use a '299 or '323. These chips don't have a separate storage register, so the RCLK signal doesn't exist. Just a suggestion. Have fun!

-- Jeff

[allisonlastname]

Dr Jefyll wrote:

But I would've though the extra flipflop you mention is required only when the VIA inputs a clock signal that's generated externally (rather than outputting a clock that's generated internally). Suggest you search the forum (or Garth's site) for doc on VIA bugs.

The flipflop thing is on Garth's circuit potpourri page, under "Using the 6522's shift register for tons of input bits". And it doesn't appear to be a bug, more a design choice that just doesn't line up with my requirements.

Quote:

Finally, your RCLK issue will disappear if you switch out the '595 and instead use a '299 or '323. These chips don't have a separate storage register, so the RCLK signal doesn't exist. Just a suggestion. Have fun!

That's almost certainly the best solution, but all I have on hand is '595s and I don't fancy putting in a parts order for a single tube of ICs. If/when I do a PCB version of Wren, I'll use different shift registers.

[gfoot]

allisonlastname wrote:

However, directly setting the value of CB2 didn't work on my test program, but it did on a smaller test that only manipulated CB2. Can you only manipulate CB2 directly when the shift register is disabled?

Yes, that's my understanding - if the shift register mode requires it to use CB2 then CB2's normal function is prevented, regardless of the state of the PCR.

You only need to trigger RCLK when you're about to read the result from the register, so you can wire it to a VIA pin and use that to latch the value before you read back from the port. You can also wire RCLK to PHI2 or something like that, in which case it will fairly frequently latch the current shift register state into the storage register - this is what I did recently in an SD card (SPI) circuit.

[Dr Jefyll]

gfoot wrote:

You can also wire RCLK to PHI2 or something like that, in which case it will fairly frequently latch the current shift register state into the storage register

Doh -- yes, of course! Good call, George.

-- Jeff