Hi all,

A quick question: I'm sure I've seen a Texas Instruments datasheet somewhere that had an example multi stage counter circuit for higher frequency counting compared to just running the ripple carry out (RCO) into the next stage counters ENT.

Am I remembering this correctly and does anyone have that datasheet or example circuit if it is possible?

Thanks!
Andrew

I found this note in the '191 datasheet


Something similar in the '163 datasheet

It's only in some of the datasheets unfortunately. See pages 21 and 22 here:
http://www.ti.com/lit/ds/symlink/sn54163.pdf

Thanks Ed and George! Those datasheets took me full circle to the post I probably originally saw on this forum. This one in particular where Dr Jefyll is commenting on one of George's posts and pointing out that the second stage ENT should just be tied high.

And I need to think about that because it seems like when the first stage hits the terminal count 0xF that RCO will go high if that first stage count enable is not controlled by ENT. And that will cause the second next stage to count if the first stage count enable is controlled by ENP. ENT and ENP are not equivalent.

Looking back at the thread I'm talking about I just realised Dr Jefyll highlighted exactly that. So I'mma stop now.

Would something like a 74HC4040 suit your purposes being a 12 bit counter?

The 4040 series are just ripple-counters internally, meaning that even within the one IC the bits don't change simultaneously - it's just a load of D flipflops chained together, with each one getting toggled by the falling edge of the one before it. I used them in some of my early circuits but this ripple causes problems at higher frequencies.

You could also consider the 74HC590 - which is 8 bits and good for fairly fast counting rates. Compared to the '163 it's twice as wide, but not presettable, and it has a built-in output register which needs to be clocked separately, and has tristate outputs so can be connected to a bus. It's a great fit for some situations, not so great for others!

I hadn't really thought about the '4040 as I'd kinda dismissed it out-of-hand for being slow and ripply. But with a bit more thought that wasn't really fair to it. Both the HCT and HC versions can run up to 80+Mhz; and I've had to put my usage of the combinatorial logic based on the counter count behind a delay to let the multiple '161s settle*.

However the propagation delay on the HCT4040 is about 8ns whereas the LVC161 is about 3ns. And that's significant as it's part of the pixel clock for an SVGA circuit; I only have about half a clock cycle (12.5ns) to make some decisions.

An LVC590 would be absolutely awesome but alas I can't even find an HCT590 and my circuit is based on TTL levels. A counter that I'm particularly fond of (and is still somewhat available) is the 74F269. It's an 8bit presttable up/down counter. Again an LVC version would be amazing.

And if I'd thought to look at the '269s datasheet before asking I would have found the answer to my '161 question. Doh.

*along with other ICs.

I think you'll find that 8ns is the propagation delay to the first output - later outputs have higher delays that may not be quoted in the datasheet. Such is life with ripple-counters!

In my video circuits I have typically used a 163 to form a memory clock by dividing the pixel clock by 4 or sometimes 8 - using its outputs to tap off various other frequencies to drive the CPU and interface circuit, and D-flipflops to shift phases as necessary - and I've used 74HCT590s for the actual addresses from that point on, e.g. one for horizontal and one or two for vertical. It's a shame if you can't find those - but in that case I think lots of 163s are your best bet, they should work well if you do the carries right, and are not too hard to hook up. The only disadvantage is that you may need additional transceivers or multiplexers to blend their outputs with addresses from the CPU when required.

I would still use separate ICs for the vertical count (it allows for easy scanline doubling, if you need it), clocked by the hsync signal rather than the pixel clock, and that is one place you can certainly use a 4040 without suffering any ill effects - especially if you use a couple of 8-bit D flipflop registers to latch its outputs, you can then clock it in the middle of the scanline, then latch its outputs at the end. The 8-bit D flipflop register can be selected to have tristate outputs as well, meaning it can connect straight to a bus in case you're not using multiplexers for that.

Overall I think this means my pixel clock doesn't really go into any of the wide counters as they're driven by outputs from earlier counters, ripple-carry-style - the pixel clock only goes to the initial 163, and to the shift registers, but not really anywhere else.